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1 of 64 rev: 021403 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description on the transmit side, the DS26102 receives atm cells from an atm device through a utopia ii interface, provides cell buffering (up to 4 cells), hec generation and insertion, cell scrambling, and converts the data to a serial stream appropriate for interfacing to a t1/e1 framer or transceiver. on the receive side, the DS26102 receives a tdm stream from a t1/e1 framer or transceiver; searches for the cell alignment; verifies the hec; provides cell filtering, descrambling, and cell buffering; and passes the cells to an atm device through the utopia ii interface. other low-level traffic management functions are selectable for the transmit and receive paths. the DS26102 can also be used in fractional t1/e1 applications. the DS26102 maps atm cells to t1/e1 tdm frames as per the atm forum specifications af-phy-0016.000 and af-phy-0064.000. in the receive direction, the cell delineation mechanism used for finding atm cell boundary within t1/e1 frame is performed as per itu i.432. the DS26102 provides a mapping solution for up to 16 t1/e1 tdm ports. the terms physical layer (phy) and line side are used synonymously in this document and refer to the device interfacing with the line side of the DS26102. the terms atm layer and system side are used synonymously and refer to the DS26102?s utopia ii interface. functional diagram features supports 16 t1/e1 tdm ports supports fractional t1/e1 compliant to atm forum specifications for atm over t1 and e1 standard utopia ii interface to the atm layer configurable utopia address range configurable tx fifo depth to 2, 3, or 4 cells optional payload scrambling in transmit direction and descrambling in receive direction per itu i.432 optional hec insertion in transmit direction with programmable coset polynomial addition hec-based cell delineation single-bit hec error correction in the receive direction receive hec-errored cell filtering receive idle/unassigned cell filtering user-definable cell filtering 8-bit mux/nonmux, motorola/intel microprocessor interface internal clock generator eliminates external high-speed clocks internal one-second timer detects/reports up to eight external status signals with interrupt support ieee 1149.1 jtag boundary scan support 17mm x 17mm, 256-pin csbga features continued on page 5. applications dslams atm over t1/e1 routers ima ordering information part temp range pin-package DS26102 -40c to +85c 256 csbga www.maxim-ic.com DS26102 16-port tdm-to-atm ph y utopia ii 16 tdm ports DS26102
DS26102 16-port tdm-to-atm phy 2 of 64 table of contents 1. features ....................................................................................................................... ...............5 2. applicable standards........................................................................................................... .5 3. acronyms and definitions.....................................................................................................6 4. block diagram .................................................................................................................. .........7 5. pin description ................................................................................................................ ..........8 6. signal definitions............................................................................................................. ......12 6.1 tdm s ignals ..........................................................................................................................12 6.2 utopia-s ide s ignals ............................................................................................................12 6.3 m icroprocessor and s ystem i nterface s ignals ................................................................14 6.4 t est and jtag s ignals .........................................................................................................16 7. transmit operation ............................................................................................................. ..17 7.1 utopia-s ide t ransmit ?m uxed m ode with 1 txclav ........................................................17 7.2 utopia-s ide t ransmit ?d irect s tatus m ode (multitxclav) .........................................19 7.3 t ransmit p rocessing ............................................................................................................20 7.4 p hysical -s ide t ransmit .........................................................................................................21 8. receive operation.............................................................................................................. ....23 8.1 p hysical -s ide r eceive ...........................................................................................................23 8.2 r eceive p rocessing ..............................................................................................................25 8.3 utopia-s ide r eceive ?m uxed m ode with 1 rxclav..........................................................27 8.4 utopia-s ide r eceive ?d irect s tatus m ode (multirxclav) ...........................................28 9. register mapping............................................................................................................... .....30 10. register definitions........................................................................................................... ...31 10.1 t ransmit r egisters ..............................................................................................................31 10.2 s tatus r egisters ..................................................................................................................35 10.3 r eceive r egisters ................................................................................................................36 11. jtag boundary scan architect ure and test access po rt....................................45 11.1 i nstruction r egister ............................................................................................................48 11.2 t est r egisters ......................................................................................................................49 12. operating parameters.........................................................................................................52 13. critical timing information................................................................................................53 14. thermal information ............................................................................................................ 59 15. applications information ...................................................................................................60 15.1 a pplication in atm u ser -n etwork i nterfaces ...................................................................60 15.2 i nterfacing with f ramers ....................................................................................................60 15.3 f ractional t1/e1 s upport ...................................................................................................61 16. package information............................................................................................................ 62 17. revision history............................................................................................................... .......64
DS26102 16-port tdm-to-atm phy 3 of 64 table of figures figure 4-1. block diagram ...................................................................................................... ................. 7 figure 7-1. polling phase and selectio n phase at transmi t interf ace.....................................................18 figure 7-2. end and restart of cell at transmit interface ...................................................................... .18 figure 7-3. transmission to phy paused for three cycles ....................................................................19 figure 7-4. example of direct status indication, transmit direction .......................................................20 figure 7-5. transmit ce ll flow and pr ocessi ng .................................................................................. ....21 figure 7-6. transmit framer in terface in tfp mode for t1.....................................................................22 figure 7-7. transmit framer interf ace in gapped-clock mode fo r t1.....................................................22 figure 7-8. transmit framer in terface in tfp mode for e1.....................................................................22 figure 7-9. transmit framer interf ace in gapped-clock mode fo r e1.....................................................23 figure 8-1. receive framer interface in rfp mode for t1 .....................................................................24 figure 8-2. receive framer interf ace in gapped-clock mode fo r t1......................................................24 figure 8-3. receive framer interface in rfp mode for e1 .....................................................................25 figure 8-4. receive framer interf ace in gapped-clock mode fo r e1......................................................25 figure 8-5. cell deli neation stat e diagr am..................................................................................... ........26 figure 8-6. header corre ction state machine.................................................................................... .....26 figure 8-7. polling phase and sele ction at receiv e interf ace.................................................................27 figure 8-8. end and restart of cell transmission at rece ive interf ace ..................................................28 figure 8-9. example direct status indication, receive direction ............................................................29 figure 10-1. accessi ng tx pmon count er......................................................................................... ....34 figure 10-2. accessing rx pmon counter s........................................................................................ ...40 figure 11-1. jtag f unctional bloc k diagram..................................................................................... ....45 figure 11-2. tap controller state diagram ...................................................................................... ......47 figure 13-1. intel bus read timing (bts = 0/mux = 1) .........................................................................53 figure 13-2. intel bus write timing (bts = 0/mux = 1) .........................................................................5 4 figure 13-3. motorola bus timing (bts = 1/mux = 1)............................................................................5 4 figure 13-4. intel bus read timing (bts = 0/mux = 0) .........................................................................55 figure 13-5. intel bus write timing (bts = 0/mux = 0) .........................................................................5 6 figure 13-6. motorola bus read timing (bts = 1/mux = 0) ..................................................................5 6 figure 13-7. motorola bus write timing (bts = 1/mux = 0) ..................................................................56 figure 13-8. setup/hold time definition ........................................................................................ .........58 figure 13-9. delay time definition ............................................................................................. ............58 figure 13-10. jtag interface timing diagram .................................................................................... ...58 figure 15-1. user-network interface application ................................................................................ ....60 figure 15-2. DS26102 interfacing with da llas framer in fram ing-pulse mode .......................................61
DS26102 16-port tdm-to-atm phy 4 of 64 list of tables table 5-a. pin description list ................................................................................................ ................ 8 table 9-a. register map........................................................................................................ .................30 table 11-a. instruction codes fo r ieee 1149.1 ar chitectu re...................................................................48 table 11-b. id code structure .................................................................................................. .............48 table 11-c. devi ce id codes .................................................................................................... .............48 table 11-d. boundary scan contro l bits ......................................................................................... .......49 table 13-a. ac characteristics?multi plexed parallel port (mux = 1)....................................................53 table 13-b. ac characteristics?nonmult iplexed parallel port (mux = 1) .............................................55 table 13-c. framer interface ac characteristics ................................................................................ ...57 table 13-d. utopia transmit ac characteristics ................................................................................. 57 table 13-e. utopia receive ac characteristics.................................................................................. .57 table 13-f. jtag interface timing.............................................................................................. ...........58 table 13-g. system clock ac characteristics.................................................................................... ....59 table 14-a. thermal properties, natural convection............................................................................. .59 table 14-b. theta-ja ( ja ) vs. airflow.....................................................................................................59 table 15-a. suggested clock edge configurations ................................................................................ 61 table 15-b. fractional t1 /e1 register settings ................................................................................. .....61
DS26102 16-port tdm-to-atm phy 5 of 64 1. features supports 16 t1/e1 ports supports fractional t1/e1 and arbitrary bit rates in multiples of 64kbps (ds0/ts) up to 2.048mbps supports clear e1 compliant to the atm forum specifications for atm over t1 and e1 standard utopia ii interface to the atm layer configurable utopia address range generic 8-bit asynchronous microprocessor interface for configuration and status indications including interrupt capability physical layer interface can accept t1/e1 tdm stream in the form of either (1) clock, data, and frame-overhead indication or (2) gapped clock (gapped at overhead positions in the frame) and data selectable active clock edge for interface with the t1/e1 framer supports diagnostic loopback optional payload scrambling in transmit direction and descrambling in receive direction as per the itu i.432 for the cell-based physical layer optional hec insertion in transmit direction with programmable coset polynomial addition option of using either idle or unassigned cells for cell-rate decoupling in transmit direction 1-byte programmable pattern for payload of cells used for cell-rate decoupling tx fifo depth configurable to either 2, 3, or 4 cells transmit fifo depth indication for 2-cell space through external pins optional single-bit hec error insertion hec-based cell delineation as per i.432 optional single-bit hec error correction in the receive direction optional filtering of hec-errored cells received optional receive idle/unassigned cell filtering optional user-defined cell filtering based on programmable header bits programmable loss-of-cell delineation (lcd) integration and interrupt interrupt for fifo overrun in receive direction saturating counts for (1) number of error-free assigned cells received and transmitted and (2) number of correctable and uncorrectable hec-errored cells received selectable internally generated clock (system clock divided by 8) in diagnostic loopback mode integrated pll generates high-frequency clocks ieee 1149.1 jtag boundary scan support 2. applicable standards [1] atm forum ?ds1 physical layer specification,? af-phy-0016.000, september 1994 [2] atm forum ?e1 physical layer specification,? af-phy-0064.000, september 1996 [3] atm forum ?utopia level 2 specification,? version 1.0, af-phy-0039.000, june 1995 [4] b-isdn user-network interface?physical layer specification?itu-t recommendation i.432?3/93
DS26102 16-port tdm-to-atm phy 6 of 64 3. acronyms and definitions acronym description atm asynchronous transfer mode crc cyclic redundancy check dpram dual port random access memory fifo first in, first out (memory) hec header error check ima inverse multiplexing for atm p microprocessor s microsecond lcd loss-of-cell delineation ms millisecond oam operations administration and maintenance ocd out-of-loss delineation pmon performance monitoring rx receive ds0 each 64kbps channel in ds1 frame ts each 64kbps channel in e1 frame (time slot) tx transmit utopia universal test and operations phy interface for atm
DS26102 16-port tdm-to-atm phy 7 of 64 4. block diagram figure 4-1. block diagram transmit tdm interface control scrambling and rate decoupling cell storage fifo transmit utopia bus interface receive tdm interface control scrambling and rate decoupling cell storage fifo receive utopia bus interface rclk0?15 rdata0?15 rfp0?15 tclk0?15 tdata0?15 tfp0?15 16 16 16 16 16 16 DS26102 controller interface jtag a 0?a6 a d0?ad7 jtclk jtdo jtdi jtms jtrst 8 7 a 7/ale (as) c s r d ( ds ) w r ( r/w ) bts mux i nt r eset rlcd0-15 16 ur-soc ur-clk ur-addr0?4 ur-data0?7 ur-clav0?3 5 8 ur-par 4 ur - en b ut-soc ut-clk ut-addr0?4 ut-data0?7 ut-clav0 ?3 5 8 ut-2clav0 ?3 ut_par 4 4 u t - en b refclkin gclkout gclkin test clock pll exstat0-7 8 8khzin 1secout 1-second timer bls0
DS26102 16-port tdm-to-atm phy 8 of 64 5. pin description table 5-a. pin description list pin name i/o function j13 1secout o one-second reference j12 8khzin i 8khz clock for one-second timer f16 a0 i p address bus bit 0 f13 a1 i p address bus bit 1 f12 a2 i p address bus bit 2 g15 a3 i p address bus bit 3 g14 a4 i p address bus bit 4 g16 a5 i p address bus bit 5 g13 a6 i p address bus bit 6 g12 a7/ale (as) i p address bus bit 7 (note 1) c14 bls0 i block select 0 c16 bts i bus type select (0 = intel) d14 cs i chip select (active low) d16 d0/ad0 i/o p data 0/address/data 0 e15 d1/ad1 i/o p data 1/address/data 1 e14 d2/ad2 i/o p data 2/address/data 2 e16 d3/ad3 i/o p data 3/address/data 3 e13 d4/ad4 i/o p data 4/address/data 4 e12 d5/ad5 i/o p data 5/address/data 5 f15 d6/ad6 i/o p data 6/address/data 6 f14 d7/ad7 i/o p data 7/address/data 7 j16 exstat0 i external status input j14 exstat1 i external status input j15 exstat2 i external status input h12 exstat3 i external status input h13 exstat4 i external status input h16 exstat5 i external status input h14 exstat6 i external status input h15 exstat7 i external status input k13 gclkin i high-frequency clock input k12 gclkout o high-frequency clock output b16 int o interrupt signal (active low) (note 2) p16 jtclk i ieee 1149.1 test clock n16 jtdi i ieee 1149.1 test data input n15 jtdo o ieee 1149.1 test data output p15 jtms i ieee 1149.1 test mode select n14 jtrst i ieee 1149.1 reset c15 mux i bus mode select (0 = nonmuxed) a1, a15, a16, b1, b2, b15, c1, c2, l16, p3, r1, r2, r15, r16, t1, t2, t16 n.c. ? no connect a14 rclk0 i rx line clock for port 0 b13 rclk1 i rx line clock for port 1 n8 rclk11 i rx line clock for port 11 p7 rclk10 i rx line clock for port 10 r8 rclk12 i rx line clock for port 12 t9 rclk13 i rx line clock for port 13 m10 rclk14 i rx line clock for port 14 p10 rclk15 i rx line clock for port 15 c12 rclk2 i rx line clock for port 2 d11 rclk3 i rx line clock for port 3 b11 rclk4 i rx line clock for port 4 a10 rclk5 i rx line clock for port 5 e9 rclk6 i rx line clock for port 6 c9 rclk7 i rx line clock for port 7
DS26102 16-port tdm-to-atm phy 9 of 64 pin name i/o function t6 rclk8 i rx line clock for port 8 m7 rclk9 i rx line clock for port 9 d15 rd ( ds ) i read enable (active low) b14 rdata0 i rx line serial data for port 0 a13 rdata1 i rx line serial data for port 1 t7 rdata10 i rx line serial data for port 10 m8 rdata11 i rx line serial data for port 11 p8 rdata12 i rx line serial data for port 12 n9 rdata13 i rx line serial data for port 13 r9 rdata14 i rx line serial data for port 14 t10 rdata15 i rx line serial data for port 15 a12 rdata2 i rx line serial data for port 2 e11 rdata3 i rx line serial data for port 3 c11 rdata4 i rx line serial data for port 4 d10 rdata5 i rx line serial data for port 5 b10 rdata6 i rx line serial data for port 6 a9 rdata7 i rx line serial data for port 7 n6 rdata8 i rx line serial data for port 8 r6 rdata9 i rx line serial data for port 9 l15 refclkin i 1.544mhz/2.048mhz reference clock l14 reset i device reset (active low) c13 rfp0 i rx frame pulse for port 0 d12 rfp1 i rx frame pulse for port 1 r7 rfp10 i rx frame pulse for port 10 t8 rfp11 i rx frame pulse for port 11 m9 rfp12 i rx frame pulse for port 12 p9 rfp13 i rx frame pulse for port 13 n10 rfp14 i rx frame pulse for port 14 r10 rfp15 i rx frame pulse for port 15 b12 rfp2 i rx frame pulse for port 2 a11 rfp3 i rx frame pulse for port 3 e10 rfp4 i rx frame pulse for port 4 c10 rfp5 i rx frame pulse for port 5 d9 rfp6 i rx frame pulse for port 6 b9 rfp7 i rx frame pulse for port 7 p6 rfp8 i rx frame pulse for port 8 n7 rfp9 i rx frame pulse for port 9 n1 rlcd0 o rx loss-of-cell delineation port 0 n2 rlcd1 o rx loss-of-cell delineation port 1 r4 rlcd10 o rx loss-of-cell delineation port 10 n5 rlcd11 o rx loss-of-cell delineation port 11 t5 rlcd12 o rx loss-of-cell delineation port 12 p5 rlcd13 o rx loss-of-cell delineation port 13 r5 rlcd14 o rx loss-of-cell delineation port 14 m6 rlcd15 o rx loss-of-cell delineation port 15 n4 rlcd2 o rx loss-of-cell delineation port 2 n3 rlcd3 o rx loss-of-cell delineation port 3 p1 rlcd4 o rx loss-of-cell delineation port 4 p2 rlcd5 o rx loss-of-cell delineation port 5 r3 rlcd6 o rx loss-of-cell delineation port 6 t3 rlcd7 o rx loss-of-cell delineation port 7 p4 rlcd8 o rx loss-of-cell delineation port 8 t4 rlcd9 o rx loss-of-cell delineation port 9 j3 ur_addr0 i rx utopia address 0 (lsb) j1 ur_addr1 i rx utopia address 1 j4 ur_addr2 i rx utopia address 2 j5 ur_addr3 i rx utopia address 3 h2 ur_addr4 i rx utopia address 4 (msb)
DS26102 16-port tdm-to-atm phy 10 of 64 pin name i/o function m5 ur_clav0 o rx utopia cell available 0 m4 ur_clav1 o rx utopia cell available 1 m1 ur_clav2 o rx utopia cell available 2 m3 ur_clav3 o rx utopia cell available 3 k5 ur_clk i rx utopia clock l3 ur_data0 o rx utopia data bus 0 (lsb) l1 ur_data1 o rx utopia data bus 1 l4 ur_data2 o rx utopia data bus 2 l5 ur_data3 o rx utopia data bus 3 k2 ur_data4 o rx utopia data bus 4 k3 ur_data5 o rx utopia data bus 5 k1 ur_data6 o rx utopia data bus 6 k4 ur_data7 o rx utopia data bus 7 (msb) j2 ur_enb i rx utopia enable (active low) m2 ur_par o rx utopia parity bit l2 ur_soc o rx utopia start of cell d8 tclk0 i tx line clock for port 0 b8 tclk1 i tx line clock for port 1 t12 tclk10 i tx line clock for port 10 t13 tclk11 i tx line clock for port 11 p13 tclk12 i tx line clock for port 12 p14 tclk13 i tx line clock for port 13 m16 tclk14 i tx line clock for port 14 l12 tclk15 i tx line clock for port 15 a7 tclk2 i tx line clock for port 2 e6 tclk3 i tx line clock for port 3 c6 tclk4 i tx line clock for port 4 d5 tclk5 i tx line clock for port 5 b5 tclk6 i tx line clock for port 6 d4 tclk7 i tx line clock for port 7 n11 tclk8 i tx line clock for port 8 r11 tclk9 i tx line clock for port 9 e8 tdata0 o tx line serial data for port 0 c8 tdata1 o tx line serial data for port 1 n12 tdata10 o tx line serial data for port 10 r12 tdata11 o tx line serial data for port 11 n13 tdata12 o tx line serial data for port 12 r14 tdata13 o tx line serial data for port 13 m13 tdata14 o tx line serial data for port 14 m15 tdata15 o tx line serial data for port 15 d7 tdata2 o tx line serial data for port 2 b7 tdata3 o tx line serial data for port 3 a6 tdata4 o tx line serial data for port 4 e5 tdata5 o tx line serial data for port 5 c5 tdata6 o tx line serial data for port 6 b4 tdata7 o tx line serial data for port 7 m11 tdata8 o tx line serial data for port 8 p11 tdata9 o tx line serial data for port 9 k16 test i test control a8 tfp0 i/o tx frame pulse for port 0 e7 tfp1 i/o tx frame pulse for port 1 p12 tfp10 i/o tx frame pulse for port 10 r13 tfp11 i/o tx frame pulse for port 11 t14 tfp12 i/o tx frame pulse for port 12 t15 tfp13 i/o tx frame pulse for port 13 m14 tfp14 i/o tx frame pulse for port 14 l13 tfp15 i/o tx frame pulse for port 15 c7 tfp2 i/o tx frame pulse for port 2
DS26102 16-port tdm-to-atm phy 11 of 64 pin name i/o function d6 tfp3 i/o tx frame pulse for port 3 b6 tfp4 i/o tx frame pulse for port 4 a5 tfp5 i/o tx frame pulse for port 5 a4 tfp6 i/o tx frame pulse for port 6 c4 tfp7 i/o tx frame pulse for port 7 t11 tfp8 i/o tx frame pulse for port 8 m12 tfp9 i/o tx frame pulse for port 9 g1 ut_2clav0 o tx utopia 2 cells available 0 h4 ut_2clav1 o tx utopia 2 cells available 1 h1 ut_2clav2 o tx utopia 2 cells available 2 h3 ut_2clav3 o tx utopia 2 cells available 3 d3 ut_addr0 i tx utopia address 0 (lsb) a2 ut_addr1 i tx utopia address 1 c3 ut_addr2 i tx utopia address 2 b3 ut_addr3 i tx utopia address 3 a3 ut_addr4 i tx utopia address 4 (msb) g4 ut_clav0 o tx utopia cell available 0 g3 ut_clav1 o tx utopia cell available 1 g2 ut_clav2 o tx utopia cell available 2 h5 ut_clav3 o tx utopia cell available 3 f2 ut_clk i tx utopia clock f1 ut_data0 i tx utopia data bus 0 (lsb) f4 ut_data1 i tx utopia data bus 1 f5 ut_data2 i tx utopia data bus 2 e2 ut_data3 i tx utopia data bus 3 e3 ut_data4 i tx utopia data bus 4 e1 ut_data5 i tx utopia data bus 5 e4 ut_data6 i tx utopia data bus 6 d2 ut_data7 i tx utopia data bus 7 (msb) d1 ut_enb i tx utopia enable (active low) g5 ut_par i tx utopia parity bit f3 ut_soc i tx utopia start of cell f8, f9, g8, g9, h6, h7, h10, h11, j6, j7, j10, j11, k8, k9, l8, l9 vdd ? positive supply f6, f7, f10, f11, g6, g7, g10, g11, h8, h9, j8, j9, k6, k7, k10, k11, k14, k15, l6, l7, l10, l11 vss ? ground d13 wr (r/w ) i write enable (active low) note 1: address-latch enable for muxed bus. note 2: open-drain output.
DS26102 16-port tdm-to-atm phy 12 of 64 6. signal definitions 6.1 tdm signals signal name: rclk0?15 signal description: receive line clock (ports 0 to 15) signal type: input the physical layer device uses the rclk input to latch the rdata and rfp signals. rdata and rfp are sampled by the receive section of the DS26102 at either the positive edge or negative edge of rclk, as controlled by the raes (rcr2.2) control bit. rclk is gapped during nonactive and framing bit positions in gapped-clock mode (rplim = 1). rclk should be glitch-free. signal name: rdata0?15 signal description: receive line data (ports 0 to 15) signal type: input the rdata input carries the receive bit stream. if the rclk is gapped at framing bit positions, rdata is then sampled at every rclk tick. if rclk is not gapped and rfp is used to indicate framing bit positions, the rdata bits that are not associated with framing-overhead bits are sampled and cell delineated. in clear e1, rdata is sampled at every rclk tick. signal name: rfp0?15 signal description: receive frame pulse (ports 0 to 15) signal type: input this active-high signal indicates the framing-overhead bit positions corresponding to rdata. for t1/e1, this aligns with the first bit of the t1/e1 frame. for t1, rdata coming at the rfp position is ignored. for e1, rfp is used to identify ts0 (rfp position is bit 0 of ts0) and ts16 locations, and rdata coming at these slots are ignored. in clear e1, rfp is ignored. in frame-pulse mode, the rfp should come once every 125 s. signal name: tclk0?15 signal description: transmit line clock (ports 0 to 15) signal type: input the tclk input is used by the DS26102?s transmit section to launch tdata and tfp (when configured as an output) at either positive edge or negative edge, as controlled by the taes (tcr2.2) control bit. signal name: tdata0?15 signal description: transmit line data (ports 0 to 15) signal type: output the tdata output carries the transmit bit stream. atm layer data bits are not transmitted during framing/overhead bit locations. tdata is output at the tclk configured active edge. signal name: tfp0?15 signal description: transmit frame pulse (ports 0 to 15) signal type: input/output this active-high signal can be set as an input or an output by using the tfsd (tcr2.0) control bit. tfp indicates the frame-overhead bit positions corresponding to tdata. for t1/e1, this signal aligns with the first bit of the t1/e1 frame. for t1, tdata coming at the tfp position does not contain valid data bit. for e1, tfp is used to identify ts0 (tfp position is bit 0 of ts0) and ts16. tdata does not contain valid data at these locations. after reset , the DS26102 is configured to use this signal as an input. in frame-pulse mode, the tfp should occur once every 125 s. 6.2 utopia-side signals signal name: ur_clk signal description: receive utopia clock signal type: input this clock is used to register and control all other utopia signals on the receive side.
DS26102 16-port tdm-to-atm phy 13 of 64 signal name: ur_addr[4:0] signal description: receive utopia address signal type: input the atm layer drives this 5-bit utopia address bus to select the appropriate utopia port. ur_addr4 is the msb and ur_addr0 is the lsb. signal name: ur_enb signal description: receive utopia enable signal type: input the atm layer asserts this active-low signal to indicate that ur_data and ur_soc are sampled at the end of the next cycle. signal name: ur_soc signal description: receive utopia start of cell signal type: output the DS26102 asserts this active-high, tri-statable signal when ur_data contains the first valid byte of a cell. ur_soc is enabled only in cycles following those with ur_enb asserted while a cell transfer is in progress. signal name: ur_data[7:0] signal description: receive utopia data bus signal type: output the DS26102 drives this byte-wide data bus in response to the selection of one of the utopia ports by the atm layer for cell transfer. this bus is three-statable, and is enabled only in cycles following those that have ur_enb asserted and a cell transfer in progress for a port. ur_data7 is the msb and ur_data0 is the lsb. signal name: ur_clav[3:0] signal description: receive utopia cell available signal type: output the active-high ur_clav signals are asserted if a complete cell is available for transfer to the atm layer for the polled port. if ur_addr does not match any of the utopia port addresses, this signal is tri-stated. ur_clav0 is driven in multiplexed with 1 clav polling mode as well as direct status mode for port 1. ur_clav3, ur_clav2, and ur_clav1 are driven only in direct status mode for ports 4, 3, and 2, respectively. signal name: ur_par signal description: receive utopia parity bit signal type: output this three-statable signal allows for parity error checking, as calculated for the 8-bits of the ur_data bus, and can represent odd or even parity as determined by the receive parity select bit (rps) in rcr1. signal name: ut_clk signal description: transmit utopia clock signal type: input this clock is used to register and control the utopia signals on the transmit side. signal name: ut_addr[4:0] signal description: transmit utopia address signal type: input the atm layer drives this 5-bit-wide bus to poll and select the appropriate utopia port. ut_addr4 is the msb and ut_addr0 is the lsb. signal name: ut_enb signal description: transmit utopia enable signal type: input the atm layer asserts this active-low enable signal during cycles when ut_data contains valid cell data.
DS26102 16-port tdm-to-atm phy 14 of 64 signal name: ut_soc signal description: transmit utopia start of cell signal type: input the atm layer asserts this active-high signal when ut_data contains the first valid byte of the cell. signal name: ut_data[7:0] signal description: transmit utopia data bus signal type: input the atm layer drives this byte-wide true data to one of the selected ports. ut_data7 is the msb and ut_data0 is the lsb. signal name: ut_clav[3:0] signal description: transmit utopia cell available signal type: output the DS26102 asserts this active-high ut_clav signal if it has cell space available to accommodate a complete cell from the atm layer to the polled port. if ut_addr does not match with any one of the utopia port addresses, this signal is tri-stated. ut_clav0 is driven in multiplexed with 1 clav polling mode as well as direct status mode for port 1. ut_clav3, ut_clav2, and ut_clav1 are driven only in direct status mode for ports 4, 3, and 2, respectively. signal name: ut_2clav[3:0] signal description: transmit utopia 2 cells available signal type: output the DS26102 asserts this active-high ut_2clav signal if it has cell space available to accommodate two complete cells from the atm layer. if ut_addr does not match with any one of the utopia port addresses, this signal is tri-stated. ut_2clav0 is driven in multiplexed with 2 clav polling mode as well as direct status mode for port 1. ut_2clav3, ut_2clav2, and ut_2clav1 are driven only in direct status mode for ports 4, 3, and 2, respectively. signal name: ut_par signal description: transmit utopia parity bit signal type: input this signal is used for parity checking as calculated for the 8 bits of the ut_data bus. transmit parity errors are reported in the port status register (psr) at bit 6. this bit can represent odd or even parity, as determined by the transmit parity select (tprs) bit in tcr1. 6.3 microprocessor and system interface signals signal name: a[6:0] signal description: microprocessor address bus signal type: input this bus selects a specific register in the DS26102 during read/write access. a7 is the msb and a0 is the lsb. a7 is also used as the address latch enable (ale/as) during multiplexed bus operation (mux = 1). signal name: a7/ale (as) signal description: address latch enable (address strobe) or a7 signal type: input in nonmultiplexed bus operation (mux = 0), the ale serves as the upper address bit. in multiplexed bus operation (mux = 1), it serves to demultiplex the bus on a positive-going edge. signal name: d[7:0]/ad[7:0] signal description: microprocessor data bus signal type: input/output this 8-bit, bidirectional data bus is used for read/write access of the DS26102?s information and control registers. d7/ad7 is the msb and d0/ad0 is the lsb. this bus also carries address information during multiplexed operation (mux = 1).
DS26102 16-port tdm-to-atm phy 15 of 64 signal name: cs signal description: chip select signal type: input this active-low signal is used to qualify register read/write accesses. the rd and wr signals are qualified with cs . signal name: rd ( ds ) signal description: read enable signal type: input along with cs, this active-low signal qualifies read access to one of the DS26102 registers. while rd and cs are both low, the DS26102 drives the d/ad bus with the contents of the addressed register. signal name: wr ( r/w ) signal description: write enable signal type: input along with cs , this active-low signal qualifies write access to one of the DS26102 registers. data at d/ad[7:0] is written into the addressed register at the rising edge of wr while cs is low. signal name: int signal description: interrupt signal type: output this active-low, open-drain output is asserted when an unmasked interrupt event is detected. int is deasserted when all interrupts have been acknowledged and serviced. signal name: mux signal description: bus operation signal type: input set this signal low to select nonmultiplexed bus operation. set it high to select multiplexed bus operation. signal name: bts signal description: bus type select signal type: input set this signal high to select motorola bus timing; set it low to select intel bus timing. this pin controls the function of the rd ( ds ), ale (as), and wr ( r/w ) pins. if bts = 1, these pins assume the function listed in parentheses (). signal name: bls0 signal description: block select 0 signal type: input this signal is available on the DS26102 to determine which octal block of ports is mapped to the microprocessor control port. signal name: refclkin signal description: reference clock signal type: input this continuous t1 (1.544mhz) or e1 (2.048mhz) clock is used to create gclkout. signal name: gclkout signal description: global clock output signal type: output this output clock is 16x the refclkin input (24.7mhz (typ) for t1). this pin is usually connected to gclkin. signal name: gclkin signal description: global clock input signal type: input this is the primary clock for internal state machines. it can be connected to gclkout or provided by the user. the gclkin frequency must be at least 10x the t1 or e1 line rate.
DS26102 16-port tdm-to-atm phy 16 of 64 signal name: reset signal description: system reset signal type: input this is an active-low reset. forcing this input low sets all internal registers to their default value. signal name: 8khzin signal description: 8khz reference clock signal type: input this continuous clock is used to generate the internal one-second-timer pulse. it can be a t1/e1 frame sync. signal name: 1secout signal description: one-second clock output signal type: output this is a one-second reference-pulse output created by dividing 8khzin by 8000. using this signal is optional. signal name: exstat0-8 signal description: external status input (1 to 8) signal type: input a low-to-high transition on this pin sets the exstat status bit in the port status register (psr). exstat1 maps to the psr for port 1 up to exstat8, which maps to port 8. the exstat bit can be enabled to generate an interrupt by setting the exstatim bit in rcr2 . these signals could be connected to an external event timer, an external status signal, or the 1secout signal generated by the DS26102. application of this signal is optional. if not used, the exstat signals should be grounded. signal name: rlcd0?15 signal description: receive loss-of-cell delineation for ports 1 to 15 signal type: output this signal is the hardware representation of the lcds status bit (psr.2). for example, if rlcd3 is high (logic 1), then port 3?s receiver has lost cell delineation (synchronization) with the incoming data stream. 6.4 test and jtag signals signal name: jtrst signal description: ieee 1149.1 test reset signal type: input jtrst is used to asynchronously reset the test access port (tap) controller. after power-up, jtrst must be toggled from low to high. this action sets the device into the jtag device id mode. pulling jtrst low restores normal device operation. jtrst is pulled high internally through a 10k ? resistor operation. if boundary scan is not used, this pin should be held low. signal name: jtms signal description: ieee 1149.1 test mode select signal type: input this pin is sampled on the rising edge of jtclk and is used to place the tap into the various defined ieee 1149.1 states. this pin has a 10k ? pullup resistor. signal name: jtclk signal description: ieee 1149.1 test clock signal signal type: input this signal is used to shift data into jtdi on the rising edge and out of jtdo on the falling edge. signal name: jtdi signal description: ieee 1149.1 test data input signal type: input test instructions and data are clocked into this pin on the rising edge of jtclk. this pin has a 10k ? pullup resistor.
DS26102 16-port tdm-to-atm phy 17 of 64 signal name: jtdo signal description: ieee 1149.1 test data output signal type: output test instructions and data are clocked out of this pin on the falling edge of jtclk. if not used, this pin should be left unconnected. signal name: test signal description: test mode signal type: input when test is set to logic 1, the refclkin input is connected to the internal sys_clk for the ip01 logic cores. in this mode, the signal on refclkin should be phase-aligned to gclkin with a frequency of gclk/2. also, when test = 1 and reset = 0, all outputs of the DS26102 should be tri-stated. 7. transmit operation the DS26102 interface to the atm layer is fully compliant to the atm forum?s utopia level 2 specification. the DS26102 supports multiplexed with 1 clav handshaking only. each octal block can be configured to use any of the address ranges (0 to 7, 8 to 15, 16 to 23, or 24 to 30) as utopia port addresses. each octal block on the bus must be configured for a different utopia address range. the depth of the tx fifo is configurable to 2, 3, or 4 cells. when a port is polled and has cell space available, the DS26102 generates a cell-available signal for that port. figure 7-1 shows the polling and cell transfer cycles to utopia ports in the DS26102. note that ut_soc must be aligned with the first byte transfer. the DS26102 uses ut_soc to detect the first byte of a cell. if a spurious ut_soc comes during a cell transfer, then the DS26102 aligns with the latest ut_soc and ignores the bytes (partial cell) received thus far. 7.1 utopia-side transmit?muxed mode with 1 txclav in level 1 utopia there is only one phy layer device. it uses ut_clav to convey transfer status to the atm layer. in level 2 utopia only one mphy port at a time is selected for a cell transfer. however, another mphy port can be polled for its ut_clav status, while the selected mphy port (device) transfers data. the atm layer polls the ut_clav status of an mphy port by placing its address on ut_addr. the mphy port (device) drives ut_clav during each cycle, following one with its address on the ut_addr lines. the atm layer selects an mphy port for transfer by placing the desired mphy port address onto ut_addr, when ut_enb is deasserted during the current clock cycle and asserted during the next clock cycle. all mphy devices only examine the value on ut_addr for selection purposes when ut_enb is deasserted. the mphy port is selected starting from the cycle after its address is on the ut_addr lines and ut_enb is deasserted; a new mphy port is addressed for selection ending in the cycle and ut_enb is deasserted. once a mphy port is selected, the cell transfer is accomplished as described by the cell-level handshake of utopia level 1. to operate an mphy device in a single phy environment, the address pins should be set to the value programmed by the management interface. figure 7-1 shows an example where phys are polled until the end of a cell transmission cycle. the ut_clav signal shows that phys n - 3 and n + 3 can accept cells and that phy n + 3 is selected. the phy is selected with the rising clock edge 16. immediately after the beginning of cell transmission to phy n + 3, the atm layer starts polling again. up to 26 phys can be polled using the 2-clock polling cycles shown in figure 7-1 . this maximum value can only be reached if all responses occur in minimum delays, e.g., as the figure shows, where the response of the last phy is obtained with clock edge 15, immediately followed by the ut_enb pulse to the phys. if an atm implementation needs additional clock cycles to select the phy, fewer than 26 phy can be polled during one cell cycle. note that if the atm decides to select phy n again for the next cell transmission, it could leave the ut_enb line asserted and start transmitting the next cell with clock edge 15. this results in back-to-back cell transmission. note that the active phy (phy n) is polled in octet p48. according to the utopia level 1 specification, the phy?s ut_clav signal at this time indicates the possibility of a subsequent cell transfer. polling of phy n before octet p44 would be possible, but it does not indicate availability of the next cell.
DS26102 16-port tdm-to-atm phy 18 of 64 figure 7-2 shows an example where the transmission of cells through the transmit interface is stopped by the atm, as no phy is ready to accept cells. polling then continues. several clock cycles later one phy gets ready to accept a cell. during the transmission pause the ut_data and ut_soc may go into high-impedance state, as shown in figure 7-2 . ut_enb is held in deasserted state. when a phy is found that is ready to accept a cell (phy_n + 3 in this case), the address of this phy must be applied again to select it. this is necessary because of the 2-clock polling cycle, where the phy is detected at clock edge 15. at this time, the address of phy n + 3 is no longer on the bus, therefore, it must be applied again in the next clock cycle. phy n + 3 is selected with clock edge 16. figure 7-1. polling phase and selection phase at transmit interface figure 7-2. end and restart of cell at transmit interface n+1 1f n-3 1f n-2 1f n-1 1f n+3 n+1 1f n 1f n+3 1f n+1 1f n-1 1f n+2 n-3 n-2 n-1 n+3 n+1 n n+3 n+1 p35 p36 p37 p38 p39 p40 p41 p42 p43 p45 p46 p47 p48 h1 h2 h3 h4 p44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ut_clk ut_addr[4:0] ut_clav[0] u t_enb ut_data[7:0] ut_soc cell xmit to: phy n phy n+3 polling polling selection n+1 1f n 1f n+3 1f n+2 1f n-1 n 1f n+3 1f n+3 1f n-2 1f n-3 1f n p45 p46 p47 p48 h1 h2 h3 h4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ut_clk ut_addr[4:0] ut_clav[0] u t_enb ut_data[7:0] ut_soc cell xmit to: phy n phy n+3 polling polling selection n+1 n n+3 n+2 n-1 n+3 n+3 n-2 detection
DS26102 16-port tdm-to-atm phy 19 of 64 figure 7-3 shows an example where the atm must pause the data transmission, as it has no data available (in this case, for three clock cycles). this is done by deasserting ut_enb and (optionally) setting ut_data and ut_soc into high-impedance state. polling may continue. in the last clock cycle, before restarting the transmission, the address ?m? of the previously selected phy is put on the ut_addr bus to reselect phy m again. figure 7-3. transmission to phy paused for three cycles 7.2 utopia-side transmit?direct status mode (multitxclav) the DS26102 supports direct status mode per af-phy-0039.000 for a maximum of four phy ports connected to one atm layer. for each phy port, the status signals ur_clav and ut_clav are permanently available, according to utopia level 1 specification. phy devices with up to four on-chip phy ports have up to four ur_clav and up to four ut_clav status signals, one pair of ur_clav and ut_clav for each phy port. status signals and cell transfers are independent of each other. no address information is needed to obtain status information. address information must be valid only for selecting a phy port prior to one or multiple cell transfers. with respect to the status signals ur_clav and ut_clav, this mode of operation corresponds to that of four individual phy devices, according to utopia level 1. with respect to the cell transfer, this mode of operation corresponds to that as described in other parts of this document. the atm layer selects a phy port for cell transfer by placing the desired port on the address lines (ur_addr[4:0], ut_addr[4:0]), while the enable signal ( ur_enb , ut_enb ) is deasserted. all phy ports only examine the value on the address lines for possible selection when the enable signal is deasserted. in case the atm suspends transmission for a specific phy port during a cell transfer, no cells to/from other phy ports can be transferred during this time. figure 7-4 shows a direct status example for the transmit direction. signals ut_clav[3:0] are associated with phy port addresses 4, 3, 2, and 1. there is no need for a unique null device, therefore, ?x = don?t care? represents any address between 0 and 31 on the address lines ut_addr[4:0] or any data on the data bus. in this mode, the DS26102 supports address ranges 0 to 3, 8 to 11, 16 to 19, or 24 to 27. in figure 7-4 the polling of phy ports starts while no cell transfer takes place. the atm layer has pending cells for all four phy ports (one individual queue for each phy port), but all four phy ports cannot accept a cell. with rising clock edge 2, phy port 1 indicates that it can accept a complete cell (ut_clav0 asserted). the atm layer detects this at clock edge 3. it selects that phy port by placing address 1 on the address lines with rising clock edge 3. phy port 1 detects this at clock edge 4. at clock edge 5, phy port 1 detects ut_enb asserted, thus cell transfer for phy port 1 starts with rising clock edge 5 (byte h1). n 1f n+1 1f n-4 1f m 1f n+2 n+3 1f 1f n n+1 n-4 m n+2 n+3 p31 p32 p33 p34 p35 p36 p38 p39 p37 1 2 3 4 5 6 7 8 9 10 11 12 13 ut_clk ut_addr[4:0] ut_clav[0] u t_enb ut_data[7:0] ut_soc cell xmit to: phy m polling phy m pause xmit polling selection
DS26102 16-port tdm-to-atm phy 20 of 64 at clock edge 5, the atm layer detects a cell available at phy port 3 (ut_clav2 asserted). with rising clock edge 52, phy port 1 indicates that it cannot accept an additional cell by deasserting ut_clav0. thus, at clock edge 57, the atm layer detects only ut_clav2 asserted (ut_clav1 and ut_clav3 remain deasserted). the atm layer deselects phy port 1 and selects phy port 3 for cell transfer with rising clock edge 57 by placing address 3 on the address lines and deasserting ut_enb . phy port 1 and phy port 3 detect this at clock edge 58. at clock edge 59, phy port 3 detects ut_enb asserted, thus cell transfer for phy port 3 starts with rising clock edge 59 (byte h1). for additional examples, refer to atm forum document af-phy-0039.000. figure 7-4. example of direct stat us indication, transmit direction 7.3 transmit processing the DS26102 can insert a valid hec byte in the cell header, or it can be programmed to transparently transmit the hec byte from atm layer. when inserting a valid hec byte, coset (0x55) addition can be disabled. the generator polynomial used is 1 + x + x 2 + x 8 . for idle/unassigned cell insertion (used for cell-rate decoupling), the DS26102 inserts a valid hec byte with or wit hout coset addition, depending on the tcrds (tcr1.3) microprocessor register bit. the DS26102 can scramble payload bytes, depending on the tpse (tcr1.4) register bit. the polynomial used for scrambling is x 43 + 1. for debugging purposes, the DS26102 can be configured to introduce a single-bit hec error in the cell header of transmitted cells. when configured in hec error-insertion mode, the DS26102 inserts hec errors in ?hec on period? number of cells and turns off hec error insertion for ?hec off period? number of cells, as set in the transmit hec error-pattern register (thepr). this process repeats periodically until hec error insertion is disabled through the theie bit (tcr1.1). n-4 1 2 3 4 5 6 53 54 55 56 57 58 ut_clk ut_addr[4:0] ut_clav0 u t_enb ut_soc 59 h1 p45 p46 p48 x p47 ut_data[7:0] x 1 x x = don't care 3 x ut_clav1 ut_clav2 ut_clav3 port 1 port 2 port 3 port 4 h2 x p44 h1 port 1 transfer port 3 52
DS26102 16-port tdm-to-atm phy 21 of 64 figure 7-5. transmit cell flow and processing 7.4 physical-side transmit the transmit framer interface operates in one of two modes: 1) gapped clock + data 2) clock + data + frame-pulse indication the mode can be selected on a per-port basis by the tplim control bit (tcr2.1). if configured in frame-pulse- indication mode, valid data bits are not sent during frame-pulse positions in the case of t1 and during ts0 and ts16 positions in case of e1 direct mapping. the ts0 and ts16 locations are identified from the frame-pulse indication signal aligned with bit 0 of the e1 frame. the tpc (tcfr.0) bit determines t1 or e1 configuration. atm cell octets are byte-aligned with respect to the frame-pulse-indication signal. in clear e1 mode, valid data bits are transmitted at every clock tick. the DS26102 can either output the frame-pulse signal or use it as an input as controlled through tfsd (tcr2.0). the active edge of the transmit clock can be selected through the taes control bit (tcr2.2). the active edge used by the transmit interface should be configured to the opposite edge of that used by the external framer. figure 7-6 shows the transmit-framer-interface operation in frame-pulse mode for t1. in this example, the DS26102 uses the positive edge of tclk to launch tdata and tfp. bit b1 is the msb of a valid cell octet and b8 is the lsb. the tfp signal should be aligned with the framing bit position. when interfacing to framers where the framing pulse and data active edges are individually configurable, it should be ensured that the sampling and updating should happen in opposite edges. utopia ii data input transmit fifo hec insertion on/off hec insertion on payload scrambling on/off hec error insertion on/off idle cell unassigned cell tcrds (tcr1.3) tcae (tcr1.2) thie (tcr1.0) tcae (tcr1.2) tpse (tcr1.4) theie (tcr1.1) honp[4:0] (thepr) hoffp[2:0] (thepr) cell data to framer (phy)
DS26102 16-port tdm-to-atm phy 22 of 64 figure 7-6. transmit framer interface in tfp mode for t1 figure 7-7 shows the transmit-framer-interface operation for t1 in gapped-clock mode. the framing overhead-bit position is gapped. in this diagram, DS26102 uses the positive edge to launch tdata. figure 7-7. transmit framer interface in gapped-clock mode for t1 figure 7-8 shows the e1 transmit-framer-interface operation using tfp to indicate the beginning of the e1 frame. the DS26102 uses the positive edge to launch tdata and tfp. using tfp, the DS26102 identifies ts0 and ts16 slots and does not send valid data on tdata in these slots. in this case, b0 to b7 are not valid data bits of a cell so that b8 is the msb of the cell octet. the timing requirements for the tfp signal are the same as in the t1 case. figure 7-8. transmit framer interface in tfp mode for e1 tclk[x] 1 tclk[x] 2 tfp[x] 3 tdata[x] 1) tclk negative edge active 2) tclk positive edge active 3) tfp as input or output dso channel 1 f b192 b191 b190 b1 b2 b3 b4 b5 b6 b7 b8 b9 tclk[x] tfp[x] tdata[x] dso channel 1 tfp is don't care f-bit gapped b191 b190 b1 b2 b3 b4 b5 b6 b7 b8 b9 b192 tclk[x] 1 tclk[x] 2 tfp[x] 3 tdata[x] 1) tclk negative edge active 2) tclk positive edge active 3) tfp as input or output (tfp_in or tfp_out) ts0 slot ts31 ts1 b0 b255 b254 b253 b1 b2 b3 b4 b5 b6 b7 b8 b9
DS26102 16-port tdm-to-atm phy 23 of 64 figure 7-9 shows the transmit framer-interface operation for e1 in gapped-clock mode. figure 7-9. transmit framer interface in gapped-clock mode for e1 the fractional t1 (n x ds0) is supported in tfp and gapped-clock modes of the physical interface. in tfp mode, the framer must generate tfp during frame-overhead-bit and nonactive-ds0-channel positions. fractional t1 is not supported if tfp is generated by the DS26102. in gapped-clock mode, tclk should be gapped during frame- overhead-bit and nonactive-ds0-channel positions. in e1, to achieve a rate in multiples of 64kbps up to 2.048mbps, the DS26102 should be configured in gapped-clock mode, and tclk should be gapped during nonactive time slots. tfp mode (for both input and output tfp configurations) is not supported in fractional e1 configuration. the DS26102 can either use the t1/e1 clock from the framer or use an internally generated low-frequency clock at the transmit line interface. the low-frequency clock is the system clock (1/2 x gclkin) divided by 8. this clock is used primarily for diagnostic loopback. the tlics bit (tcr2.6) selects between the framer clock and the internally generated clock. the internally generated clock should be used only in diagnostic loopback (other wise, the framer and DS26102 are operating for different clocks). during diagnostic loopback, this clock is fed to the receive line interface unit. 8. receive operation the receive interface of the DS26102 is fully compliant to the atm forum?s utopia level 2 specifications. each octal block of the DS26102 can be configured to use one of the address ranges (0 to 7, 8 to 15, 16 to 23, and 24 to 30) as utopia port addresses. if rx fifo is not empty, cell available is asserted. after cell transfer from a port, the external cell-available signal is updated based on the receive-fifo fill level one clock cycle after cell transfer completion. during this one-clock cycle, cell-available indication for this port is kept in the deasserted state. in other words, one-clock minimum latency between two cell transfers from the same utopia port is needed by the DS26102 to update its internal cell pointers. section 8.3 gives additional details concerning the utopia-side interface. 8.1 physical-side receive the receive framer interface operates in one of two modes: 1) gapped clock + data 2) clock + data + frame-pulse indication the mode can be selected on a per-port basis with the receive physical-layer interface mode control bit (rplim) at rcr2.1. if configured in frame-pulse-indication mode, t he bits coming at frame-pulse-indication positions are ignored in case of t1 direct mapping, and bits coming at ts0 and ts16 positions are ignored in case of e1 direct mapping. ts0 and ts16 slots are identified using the frame-pulse indication aligned with bit 0 of the e1 frame. the control bit rpc (rcfr.0) determines t1 or e1 configuration. if no frame-pulse indication is given, bits are sampled at every receive clock tick. if clear e1 operation is needed, the interface should be configured to operate in gapped tclk[x] tfp[x] tdata[x] ts31 tfp is don't care ts0 (gapped) ts1 b254 b8 b9 b10 b255
DS26102 16-port tdm-to-atm phy 24 of 64 clock + data mode, in which case the external frame-pulse-indication signal is ignored and the data bits are clocked at every clock tick. the active edge of the receive clock can be selected through the raes (rcr2.2) control bit. the active edge selected for the rx framer interface should be opposite the active edge that is used by the transmitting device (either an external framer or the transmit section of DS26102, when enabled for diagnostic loopback). diagnostic loopback toward the atm layer side (utopia side) can be enabled through the dlbe (rcr2.0) control bit. in diagnostic loopback, data, clock, and frame-pulse indication generated by the transmit section of the DS26102 are used instead of the corresponding signals from the physical layer device. rx physical-interface mode should be configured with same value as the tx physical-interface mode. the rx active-edge selection bit should be configured as the opposite edge of that used by the transmit section of the DS26102. figure 8-1 shows the receive framer-interface operation for t1 mode with the DS26102 using the positive clock edge to sample rdata and rfp and the framer using the negative edge to launch rdata and rfp. figure 8-1. receive framer interface in rfp mode for t1 figure 8-2 shows the receive-framer-interface operation for t1 in gapped-clock mode. the framing overhead-bit position is gapped. in this figure, the DS26102 uses the positive edge to sample rdata and rfp. rfp is don?t care. figure 8-2. receive framer interface in gapped-clock mode for t1 figure 8-3 shows the receive-framer-interface operation for e1 using rfp to indicate the beginning of the e1 frame. the DS26102 uses the positive edge of rclk to sample rdata and rfp. using rfp, the DS26102 identifies ts0 and ts16 slots and ignores rdata coming in these slots. rclk[x] rfp[x] rdata[x] dso channel 1 f b192 b191 b190 b1 b2 b3 b4 b5 b6 b7 b8 b9 rclk[x] rdata[x] dso channel 1 f-bit gapped b192 b191 b190 b1 b2 b3 b4 b5 b6 b7 b8 b9
DS26102 16-port tdm-to-atm phy 25 of 64 figure 8-3. receive framer interface in rfp mode for e1 figure 8-4 shows the receive-framer-interface operation for e1 in gapped-clock mode. in this mode, rclk is gapped during ts0 and ts16 locations. figure 8-4. receive framer interface in gapped-clock mode for e1 the fractional t1 (n x ds0) is supported in both rfp and gapped-clock modes of physical interface. in rfp mode, the framer must generate rfp during frame-overhead-bit and nonactive-ds0-channel positions. in gapped-clock mode, rclk should be gapped during frame-overhead-bit and nonactive-ds0-channel positions. in e1 mode, the DS26102 should be configured in gapped-clock mode and rclk should be gapped during nonactive time slots. rfp mode is not supported in fractional e1 configuration. 8.2 receive processing the received bits, after ignoring framing-overhead bits, are checked for possible hec pattern. the polynomial used for hec check is g(x) = 1 + x + x 2 + x 8 , per itu i.432. clearing the microprocessor interface register bit rcse (rcr1.0) can disable the coset subtraction (0x55). the cell boundaries in the incoming bit stream are identified based on hec. figure 8-5 shows the cell-delineation state machine. the cell-delineation state machine is initially in hunt state. in hunt state, it performs bit-by-bit hunting for correct hec. if correct hec is found, it transitions to the presync state where it checks cell-by-cell for correct hec patterns. if delta-consecutive-correct patterns are received in presync, the cell-delineation state machine transitions to sync state. otherwise, it goes to hunt state and reinitiates bit-by-bit hunting. in sync state, if alpha-consecutive-incorrect hec patterns are rece ived, cell delineation is lost and it goes to hunt state. in presync and sync states, only cell-by-cell checking for the proper hec pattern is performed. for the DS26102, alpha = 7 and delta = 6. the persistence of the out-of-cell delineation (ocd) event is integrated into lcd, based on programmable integration time period (rx-lcd integration-period register). if ocd persists for the programmed time, lcd is declared. lcd is deasserted only when cell delineation persists in sync for the same-programmed integration time. whenever there is a change in lcd status (namely ?into lcd? or ?out of lcd?), an external interrupt is generated when enabled by the corresponding mask bit rcr2.4. the persistence is checked every system clock period (sys_clk) divided by 16,383. the default value of the rx lcd integration-period register provides for an integration time of 100ms for a 16.5mhz sys_clk. rclk[x] rfp[x] rdata[x] ts0 slot ts31 ts1 b0 b255 b254 b253 b1 b2 b3 b4 b5 b6 b7 b8 b9 rclk[x] rdata[x] ts31 ts0 (gapped) ts1 b8 b9 b10 b255 b254 don't care
DS26102 16-port tdm-to-atm phy 26 of 64 if single-bit header-error correction is enabled, the receiver mode of operation state machine follows the state machine given in figure 8-6 . single-bit correction is done only if correction is enabled and the state machine is in the correction mode of operation at the start of cell transfer. receiver mode of operation is valid only when cell delineation is in sync state. the DS26102 maintains 8-bit correctable and 12-bit uncorrectable hec-errored cell counts. both of these counters saturate. figure 8-5. cell delineation state diagram figure 8-6. header correction state machine hec error correction is performed based on receiver mode of operation. in correction mode, only single bit errors can be corrected and the receiver switches to detection mode. in detection mode, all cells with detected header errors are discarded, provided the receive-pass hec-errored cells (rphec) control bit (rcr1.3) is clear. when a header is examined and found not to be in error, the receiver switches to correction mode. the term ?no action? in figure 8-6 means no correction is performed and no cell is discarded. the payload bytes of the cell are descrambled using the self-synchronizing descrambler polynomial x 43 + 1, as given in itu-t i.432. the descrambling can be enabled through the rde control bit (rcr1.2). descrambling is activated if cell delineation is in presync or sync state. the cell header is not affected by descrambling. hunt presync sync bit by bit correct hec incorrect hec cell by cell delta consecutive correct hec alpha consecutive incorrect hec cell by cell correction mode detection mode multibit error detected (cell discarded) single bit error detected (correction) no error detected (no action) no error detected (no action) error detected (cell discarded)
DS26102 16-port tdm-to-atm phy 27 of 64 after descrambling and single-bit header-error correction, the cells are written into the receive fifo as long as cell delineation is in sync and the rx fifo is not full. idle and/or unassigned cells can be filtered when enabled in the receive control registers. uncorrectable hec-errored cells are normally filtered and are not written into the rx fifo unless rphec (rcr1.3) is set. note that if hec error corre ction is disabled, all hec-errored cells are termed as uncorrectable hec-errored cells. a 16-bit counter tracks the number of cells that can be written into the rx fifo and saturates at 0xffff. note that, whether or not the atm layer dequeues cells from rx fifo, this counter is incremented if valid cells are received. this counter is cleared by the microprocessor interface once it is latched. a 4-cell buffer per port is maintained for rate decoupling. 8.3 utopia-side receive?muxed mode with 1 rxclav an internal version of the cell-available signal is maintained per port. the DS26102 drives the internal cell-available signals onto the external clav lines based on the configured polling mode. in direct status mode, only four ports are supported. the four external clav lines are driven with the corresponding internal clav signals for utopia ports 0 to 3. in multiplexed-with-1-clav mode, only clav [0] is driven with the cell-available signal for the port corresponding to the current lower three utopia address bits. the upper two utopia address bits should match the configured address range. if cell transfer is going on for a port, its clav is kept asserted until the last byte is transferred to the atm layer. this is accomplished to support interfacing with the octet-level atm layer as well. the atm layer must poll cell-available status for any fresh cell corresponding to a port only after the current cell transfer to the port is completed. the multiplexed with 1 clav polling-mode cycle is depicted in figure 8-7 , in which n, n + 2, n - 3, n - 2, n - 1, n + 3, n + 1 are considered part of the DS26102 utopia ports. during reception of a cell from phy n, the other phys are polled. it turns out that phy n - 3 and phy n + 3 have cells available, and phy n + 3 is ultimately selected. just like the transmit interface, the 2-clock polling cycle allows a maximum of 26 phys to be polled in the 8-bit mode during a cell transfer. figure 8-7. polling phase and selection at receive interface figure 8-8 shows a case when, after the end of transmission of a cell from phy n, no other phy has a cell available. therefore, ur_enb remains asserted as the atm assumes a cell available from phy n. with clock edge 9, phy n also has no cell available, as ur_soc remains low. the atm then deasserts ur_enb while the polling of the phys continues. with clock edge 15, phy n - 3 is found to have a cell for transmission. so address n - 3 is applied, and the phy n - 3 is selected with clock edge 16. additional receive interface examples are available in atm forum?s af-phy-0039.000. n+2 1f n-3 1f n-2 1f n-1 1f n+3 n+1 1f n-1 1f n+3 1f n+1 1f n-1 1f n+2 n-3 n-2 n-1 n+3 n+1 n+3 n+1 p35 p36 p37 p38 p39 p40 p41 p42 p43 p45 p46 p47 p48 h1 h2 h3 p44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ur_clk ur_addr[4:0] ur_clav[0] u r_enb ur_data[7:0] ur_soc cell rcv from: phy n phy n+3 polling polling selection n-1
DS26102 16-port tdm-to-atm phy 28 of 64 figure 8-8. end and restart of cell transmission at receive interface 8.4 utopia-side receive?direct status mode (multirxclav) consider up to a maximum of four phy ports connected to one atm layer. for each phy port, the status signals ur_clav and ut_clav are permanently available according to utopia level 1 specification. phy devices with up to four on-chip phy ports have up to four ur_clav and up to four ut_clav status signals, one pair of ur_clav and ut_clav for each phy port. status signals and cell transfers are independent of each other. no address information is needed to obtain status information. address information must be valid only for selecting a phy port prior to one or multiple cell transfers. with respect to the status signals ur_clav and ut_clav, this mode of operation corresponds to that of four individual phy devices, according to utopia level 1. with respect to the cell transfer, this mode of operation corresponds to that described in this document and af-phy-0039.000. the atm layer selects a phy port for cell transfer by placing the desired port on the address li nes (ur_addr[4:0], ut_addr[4:0]), while the enable signal ( ur_enb , ut_enb ) is deasserted. all phy ports only examine the value on the address lines for possible selection when the enable signal is deasserted. if the atm layer suspends transmission for a specific phy port during a cell transfer, no cells to/from other phy ports can be transferred during this time. figure 8-9 shows an example for the receive direction. the status signals ur_clav[3:0] are associated with phy port addresses 4, 3, 2, and 1. note that for the DS26102, the address range can be any one of 0 to 3, 8 to 11, 16 to 19, and 24 to 27. there is no need for a unique null device, so ?x = don?t care? on the address lines ur_addr[4:0]. in figure 8-9 the polling of phy ports starts while no cell transfer takes place. the atm layer monitors all four status signals ur_clav[3:0]. at clock edge 3, it detects a cell available at phy port 1 (ur_clav0 asserted). it selects that phy port by placing address 1 on the address lines with rising clock edge 3. phy port 1 detects this at clock edge 4. at clock edge 5, phy port 1 detects ur_enb asserted, thus cell transfer for phy port 1 starts with rising clock edge 5. at clock edge 5, the atm layer detects a cell available at phy port 3 (ur_clav2 asserted). not knowing whether phy port 1 may have another cell available or not, the atm layer deselects phy port 1 and selects phy port 3 for cell transfer with rising clock edge 57 by placing address 3 on the address lines and deasserting ur_enb. phy port 1 and phy port 3 detect this at clock edge 58. at clock edge 59, phy port 3 detects ur_enb asserted, thus cell transfer starts with rising clock edge 59. at clock edge 111, no cell is available at phy ports 1, 2, and 4. the atm layer keeps ur_enb asserted and detects at clock edge 113 the first byte of another cell available from phy port 3 (ur_clav2 asserted). thus, cell transfer takes place starting with rising clock edge 112. at clock edge 164, again, no cell is available at phy ports 1, 2, and 4. the atm layer keeps the ur_enb asserted and detects at n-3 1f n+1 1f n-1 1f n 1f n+3 n-1 1f n-3 1f n-3 1f n+1 1f n+2 1f n-1 h1 h2 h3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ur_clk ur_ addr [4:0] ur_clav[0] u r_enb ur_data[7:0] ur_soc cell rcv from: phy n phy n-3 polling polling selection n-3 n+1 n-1 n n+3 n-3 n-3 n+1 detection p45 p46 p47 p48 p42 p43 p44 xx
DS26102 16-port tdm-to-atm phy 29 of 64 clock edge 166 that there also is no cell available from phy port 3 (ur_clav2 deasserted). thus, the atm layer deselects phy port 3 by deasserting ur_enb with rising clock edge 166. figure 8-9. example direct status indication, receive direction 1 2 3 4 5 6 58 59 60 112 113 ur_clk ur_addr[4:0] ur_clav0 u r_enb ur_soc 114 h1 h1 p48 h1 ur_data[7:0] x 1 x ur_clav1 ur_clav2 ur_clav3 port 1 port 2 port 3 port 4 p48 h2 57 165 166 167 111 164 3 x x x tri-stated p48 x cell transfer (port 1) cell transfer (port 3) cell transfer (port 3)
DS26102 16-port tdm-to-atm phy 30 of 64 9. register mapping the 8-bit registers described in this section are maintained per port, unless otherwise noted. address bits [7:5] determine port number, address bit [4] distinguishes tx and rx section registers, and address bits [3:0] select the particular register in tx and rx sections. this register arrangement applies to each block of eight t1/e1 ports. the DS26102 contains two octal blocks that are selected with the bls signal. table 9-a. register map p1 p2 p3 p4 p5 p6 p7 p8 r/w register function 00 ? ? ? ? ? ? ? rw tcfr tx configuration register (note 1) ? 20 40 60 80 a0 c0 e0 ? ? reserved (note 2) 01 21 41 61 81 a1 c1 e1 w tpcl tx pmon counter latch-enable register 02 22 42 62 82 a2 c2 e2 r tacc1 tx-assigned cell counter msb (note 3) 03 23 43 63 83 a3 c3 e3 r tacc2 tx-assigned cell counter lsb (note 4) 04 ? ? ? ? ? ? ? rw tiupb tx idle/unassigned payload byte (note 1) ? 24 44 64 84 a4 c4 e4 ? ? reserved (note 2) 05 ? ? ? ? ? ? ? rw thepr tx hec error-insertion pattern (note 1) ? 25 45 65 85 a5 c5 e5 ? ? reserved (note 2) 06 26 46 66 86 a6 c6 e6 rw tcr1 tx control register 1 07 27 47 67 87 a7 c7 e7 rw tcr2 tx control register 2 08 ? ? ? ? ? ? ? r isr interrupt status register (note 1) 09 to 0f 28 to 2f 48 to 4f 68 to 6f 88 to 8f a8 to af c8 to cf e8 to ef ? ? reserved (note 2) 10 ? ? ? ? ? ? ? rw rcfr rx configuration register (note 1) ? 30 50 70 90 b0 d0 f0 reserved 11 ? ? ? ? ? ? ? rw rlcdip rx lcd integration register (note 1) ? 31 51 71 91 b1 d1 f1 ? ? reserved 12 32 52 72 92 b2 d2 f2 w rpcl rx pmon counter-latch enable 13 33 53 73 93 b3 d3 f3 r rchec rx correctable hec latch 14 34 54 74 94 b4 d4 f4 r ruhec1 rx uncorrectable hec msb 15 35 55 75 95 b5 d5 f5 r ruhec2 rx uncorrectable hec lsb 16 36 56 76 96 b6 d6 f6 r racc1 rx-assigned cell counter msb (note 5) 17 37 57 77 97 b7 d7 f7 r racc2 rx-assigned cell counter lsb (note 6) 18 38 58 78 98 b8 d8 f8 r psr per port status register 19 39 59 79 99 b9 d9 f9 rw rcr1 rx control register 1 1a 3a 5a 7a 9a ba da fa rw rcr2 rx control register 2 1b 3b 5b 7b 9b bb db fb rw rufc rx user-filter control 1c 3c 5c 7c 9c bc dc fc rw rufpm1 rx user-filter pattern/mask 1 1d 3d 5d 7d 9d bd dd fd rw rufpm2 rx user-filter pattern/mask 2 1e 3e 5e 7e 9e be de fe rw rufpm3 rx user-filter pattern/mask 3 1f 3f 5f 7f 9f bf df ff rw rufpm4 rx user-filter pattern/mask 4 p1 to p8 = address locations (hex) for utopia phy port 1 through port 8. note 1: these registers are common to all ports. note 2: writing into reserved address regions should be avoided. reading from reserved address regions could give undefined value. note 3: tx-assigned cell counter msb-latch register is an 8-bit register common to all ports. it can be accessed with any of the 8 addr esses. this register holds the upper 8-bit of the tx-assigned-cell count for the port selected by accessing the tx-pmon counter latch- enable register. note 4: tx-assigned cell counter lsb-latch register is an 8-bit register common to all ports. it can be accessed with any of the 8 addr esses. this register holds the lower 8-bit of the tx-assigned cell count for the port selected by accessing the tx-pmon counter latch- enable register. note 5: rx-assigned cell counter msb-latch register is an 8-bit register common to all ports. it can be accessed with any of the 8 addr esses. this register holds the upper 8-bit of the rx-assigned cell count for the port selected by accessing the rx-pmon counter latch- enable register. note 6: rx-assigned cell counter lsb-latch register is an 8-bit register common to all ports. it can be accessed with any of the 8 addr esses. this register holds the lower 8-bit of the rx-assigned cell count for the port selected by accessing the rx-pmon counter latch- enable register. conventions: 1) in bit definitions, bit 7 is the most significant bit (msb) and bit 0 is the least significant bit (lsb). 2) ports can be referred with either 1 to 8 (one-based) or 0 to 7 (zero-based). while referring a port, the addressing system, either one-based or zero-based is explicitly mentioned in brackets.
DS26102 16-port tdm-to-atm phy 31 of 64 3) reserved bit fields should be replaced with 0 while writing and, upon reading, the value corresponding to reserved bit field s is undefined. 4) r indicates read permission; w indicates write permission; rw indicates read/write permission for software to access a regis ter. 10. register definitions 10.1 transmit registers register name: tcfr register description: transmit configuration register register address: 00h (common for all transmit ports) bit: 7 6 5 4 3 2 1 0 name: ? ? ? ? taddr1 taddr0 tpm tpc default: 0 0 0 1 0 0 0 0 bit 0: transmit port configuration (tpc). this bit affects only the tx section. 0 = t1 mode 1 = e1 mode bit 1: transmit poll mode (tpm). transmit utopia polling mode configuration. 0 = multiplexed with 1clav mode 1 = direct status bits 2, 3: transmit high address (taddr). these bits decide which upper 2 bits of the utopia address are to be used by the atm layer for selecting one of the ports. the lower 3 bits of address are assigned to the port number 1 to 8 (one-based): '00' for address range 0?7 '01' for address range 8?15 '10' for address range 16?23 '11' for address range 24?30 * note that the address range selected when the bsl0 pin = 0 must be different than the address range selected when bsl0 = 1. bits 3 to 7: unassigned, read only * address 31 (1f hex) is reserved as the null address per utopia forum. when an octal block is offset to the highest utopia addre ss range, the port at address 31 becomes inactive.
DS26102 16-port tdm-to-atm phy 32 of 64 register name: tcr1 register description: transmit control register 1 register address: 06h, 26h, 46h, 66h, 86h, a6h, c6, e6h bit: 7 6 5 4 3 2 1 0 name: ? tpedim tprs tpse tcrds tcae theie thie default: 0 0 0 0 0 1 0 1 bit 0: transmit hec insertion enable (thie) 0 = hec byte as received from the atm layer is transparently passed. 1 = proper hec value is computed and inserted into the hec byte of the cell. bit 1: transmit hec error-insertion enable (theie) 0 = hec error insertion disabled 1 = hec errors are introduced into the transmitted cells, as specified by the transmit hec error-insertion pattern register. bit 2: transmit coset addition enable (tcae) 0 = no coset addition 1 = coset (0x55) addition to the calculated hec. note that if hec insertion is disabled, the hec byte is transmitted transparently (this bit does not affect atm layer cells). however, the hec byte of idle/unassigned cells used for cell-rate decoupling includes coset addition as long as the tcae bit is enabled. bit 3: transmit cell-rate decoupling selection (tcrds) 0 = idle cell 1 = unassigned cell bit 4: transmit payload scrambling enable (tpse) 0 = disable scrambling 1 = enable scrambling bit 5: transmit parity select (tprs). this bit determines the parity mode expected on the ut_par signal. 0 = odd parity check selected for transmit utopia bus 1 = even parity check selected for transmit utopia bus bit 6: transmit parity error-detect interrupt mask (tpedim) 0 = DS26102 does not generate an external interrupt on a tx parity error. 1 = DS26102 does generate an external interrupt on a tx parity error. bit 7: unassigned, must be set to 0 for proper operation
DS26102 16-port tdm-to-atm phy 33 of 64 register name: tcr2 register description: transmit control register 2 register address: 07h, 27h, 47h, 67h, 87h, a7h, c7h, e7h bit: 7 6 5 4 3 2 1 0 name: ? tlics fdc1 fdc0 tces taes tplim tfsd default: 0 0 0 0 0 0 0 0 bit 0: transmit frame-sync direction (tfsd) 0 = utopia block accepts a transmit frame sync (tfp is an input). 1 = utopia block generates a frame sync (tfp is an output). bit 1: transmit physical-layer interface mode (tplim) 0 = clock + data + frame-pulse-indication combination 1 = gapped clock + data combination bit 2: transmit active-edge selection (taes) 0 = positive edge of tclk as timing reference 1 = negative edge of tclk as timing reference bit 3: transmit clear e1 selection (tces) 0 = channelized e1 (data at ts0 and ts16 is ignored) 1 = clear e1 (all e1 channels are used) bits 4, 5: transmit fifo depth configuration bits (fdc1, fdc0) fdc1 fdc0 cell depth 0 0 4 0 1 3 1 0 2 1 1 reserved bit 6: transmit line interface clock selection (tlics) 0 = the t1/e1 clock from the framer (tclkx) is used at the transmit line interface. 1 = the internally generated system clock divided by 8 is used at the transmit line interface. bit 7: unassigned, must be set to 0 for proper operation register name: tpcl register description: transmit pmon counter latch register address: 01h, 21h, 41h, 61h, 81h, a1h, c1h, e1h bit: 7 6 5 4 3 2 1 0 name: ? ? ? ? ? ? ? ? default: 0 0 0 0 0 0 0 0 bits 0 to 7: the host should always write 0x00 to this register when latching the pmon counter. this register is provided for latching in the 16-bit transmit-assigned cell-count value of a port into the common transmit- assigned cell-counter latch register. in order to read the transmit-assigned cell-count value, software writes into this register and then reads from the tx-assigned cell counter msb and lsb registers. a write into this register clears the value. figure 10-1 depicts the sequence of operation for accessing the tx-assigned cell counter (tacc) for a given port.
DS26102 16-port tdm-to-atm phy 34 of 64 figure 10-1. accessing tx pmon counter register name: tacc1 register description: transmit-assigned cell-count register 1 register address: 02h, 22h, 42h, 62h, 82h, a2h, c2h, e2h (common to all ports) bit: 7 6 5 4 3 2 1 0 name: tacc15 tacc14 tacc13 tacc12 tacc11 tacc10 tacc9 tacc8 default: 0 0 0 0 0 0 0 0 bits 0 to 7: transmit-assigned cell count (tacc8 to tacc15). this register is read-only. register name: tacc2 register description: transmit-assigned cell-count register 2 register address: 03h, 23h, 43h, 63h, 83h, a3h, c3h, e3h (common to all ports) bit 7 6 5 4 3 2 1 0 name tacc7 tacc6 tacc5 tacc4 tacc3 tacc2 tacc1 tacc0 default 0 0 0 0 0 0 0 0 bits 0 to 7: transmit-assigned cell count (tacc0 to tacc7). this register is read-only. these registers are common for all ports. for software convenience, any of the eight addresses can be used to access these registers. the transmit-assigned cell-count value reflects the number of atm layer cells transmitted since last latching. for reading the 16-bit transmit-assigned cell count for a port, software must write into the transmit-pmon counter latch- enable register for the desired port prior to reading these registers. reading from these registers without writing into the latch-enable register returns the old value that was latched and not the current value. what the host must do how the ds26101/DS26102 responds ds26101/DS26102 latches tx-assigned cell-counter value of the port selected into corresponding latch register and clears the internal a ssigned cell counter of the port for fresh accumulation. ds26101/DS26102 drives most significant 8 bits (tacc[15:8]) of latched assigned cell-count value onto the data bus. ds26101/DS26102 drives least significant 8 bits (tacc[7:0]) of latched assigned cell-count value onto the data bus. write 00 into tx-pmon counter latch register (tpcl) for the port whose counter value is to be obtained. note that only the address specific to the port intended must be used. read from tx-assigned cell counte r latch register 1 (tacc1). note that a ny one of the eight addresses specified for this register can be used. read from tx-assigned cell counte r latch register 2 (tacc2). note that a ny one of the eight addresses specified for this register can be used.
DS26102 16-port tdm-to-atm phy 35 of 64 register name: tiupb register description: transmit idle/unassigned payload byte register register address: 04h (common for all transmit ports) bit: 7 6 5 4 3 2 1 0 name: tiup7 tiup6 tiup5 tiup 4 tiup3 tiup2 tiup1 tiup0 default: 0 1 1 0 1 0 1 0 bits 0 to 7: transmit idle/unassigned payload (tiup0 to tiup7). this register holds the payload byte to be carried in octets of idle/unassigned cells, transmitted toward the line for cell-rate decoupling. this register defaults to the value 6ah. register name: thepr register description: transmit hec er ror-insertion pattern register register address: 05h (common for all transmit ports) bit: 7 6 5 4 3 2 1 0 name: hoffp4 hoffp3 hoffp2 hoffp 1 hoffp0 honp2 honp1 honp0 default: 0 0 1 0 1 0 0 1 bits 0 to 2: hec on period (honp0 to honp2). this register holds the number of cells in which incorrect hec (hec error insertion is on) is sent, if hec error insertion is enabled. bits 3 to 7: hec off period (hoffp0 to hoffp4). this register holds the number of cells in which correct hec (hec error insertion is off) is sent, if hec error insertion is enabled. if hec error insertion in the transmit control register is enabled for a port (theie = 1), then for the ?hec off period? cells are transmitted to the port with correct hec; for the ?hec on period? cells are sent with incorrect hec. this cycle repeats until hec error insertion is disabled. note that hec errors are inserted according to the above pattern as long as theie is set, whether hec insertion (thie) is enabled or not. 10.2 status registers register name: psr register description: port status register register address: 18h, 38h, 58h, 78h, 98h, b8h, d8h, f8h bit: 7 6 5 4 3 2 1 0 name: exstat tped cds1 cds0 rms lcds lcdcsis fois default: 0 0 0 0 0 1 0 0 bit 0: receive fifo-overrun interrupt status (fois). this status bit is set when the receive fifo overruns. it creates an interrupt on the int pin if the rx fifo-overrun interrupt mask bit (rcr2.3) is set. this bit is reset when read. bit 1: lcd change -of-state interrupt status (lcdcsis). this status bit is set when lcd status changes. it creates an interrupt on the int pin if the lcd interrupt mask bit (rcr2.4) is set. this bit is reset when read. bit 2: lcd status (lcds). the lcds bit indicates the current status of lcd. 0 = in-cell delineation 1 = loss-of-cell delineation bit 3: receiver mode status (rms). this bit shows valid status only when hec correction is enabled. 0 = correction mode 1 = detection mode
DS26102 16-port tdm-to-atm phy 36 of 64 bits 4, 5: cell delineation status 0, 1 (cds0, cds1). these bits show the cell delineation status. bit 5 indicates instantaneous ocd status. cds1 cds0 cell delineation status 0 0 hunt state 0 1 presync state 1 x sync state bit 6: transmit parity error detect (tped). this bit is set for each transmit parity error that is detected on the transmit utopia interface. it can generate an interrupt when enabled by tpedim in tcr1. this bit is reset if read access to this register is detected. bit 7: external status event (exstat). this bit is set on the rising edge of the signal applied to the associated exstat signal. it can generate an interrupt when enabled by exstatim in rcr2. this bit is reset if read access to this register is detected. exstat1 maps to this bit in the psr for port 1 (18h) up to exstat8, which maps to the psr for port 8 (f8h). a typical application might connect the 1secout signal created by the DS26102 to one of the exstat signals so that an interrupt can be created on 1-second boundaries. the exstat signals, however, can also be used to provide microprocessor access to board-level hardware-status pins or an off-chip interval timer. register name: isr register description: interrupt status register register address: 08h (common for all ports) bit: 7 6 5 4 3 2 1 0 name: psr8 psr7 psr6 psr5 psr4 psr3 psr2 psr1 default: 0 0 0 0 0 0 0 0 the isr register reports which of the 8 ports are currently generating interrupts. isr.0 reports the status for port 1 (18h), while isr.7 reports the status for port 8 (f8h). when the associated port?s status register is read (and consequently cleared), the associated bit in this register is also cleared. note that only status bits that are enabled to generate an interrupt (i.e., the interrupt mask bi t is set) set the reporting bit in this register. 10.3 receive registers register name: rcfr register description: receive configuration register register address: 10h (common for all receive ports) bit: 7 6 5 4 3 2 1 0 name: ? ? ? ? raddr1 raddr0 rupm rpc default: 0 0 0 1 0 0 0 0 bit 0: receive port configuration (rpc). this bit affects only the rx section. 0 = t1 mode 1 = e1 mode bit 1: receive polling mode (rupm) 0 = multiplexed with 1clav mode 1 = direct status bits 2, 3: receive high address (raddr). these bits decide which upper 2 bits of the utopia address are to be used by the atm layer for selecting one of the ports. the lower 3 bits of address are assigned to port number 1 to 8 (one-based): '00' for address range 0?7 '01' for address range 8?15
DS26102 16-port tdm-to-atm phy 37 of 64 '10' for address range 16?23 '11' for address range 24?30 * note that the address range selected when the bsl0 pin = 0 must be different than the address range selected when bsl0 = 1. bits 4 to 7: unassigned, read only * address 31 (1f hex) is reserved as the null address per utopia forum. when an octal block is offset to the highest utopia addre ss range, the port at address 31 becomes inactive. register name: rcr1 register description: receive control register 1 register address: 19h, 39h, 59h, 79h, 99h, b9h, d9h, f9h bit: 7 6 5 4 3 2 1 0 name: ? rprs rucfe ricfe rphec rde rhece rcse default: 0 0 0 0 0 0 0 1 bit 0: receive coset subtraction enable (rcse) 0 = DS26102 does not do coset subtraction from hec byte for checking hec. 1 = DS26102 subtracts coset polynomial (0x55) from the hec byte for checking hec. bit 1: receive hec error- correction enable (rhece) 0 = single-bit hec error correction is disabled. 1 = the DS26102 corrects single-bit hec errors based on the current state of receiver mode of operation. single-bit error correction is done only if this bit is set and the receiver mode of operation is in correction state. bit 2: receive descrambling enable (rde) 0 = payload descrambling is disabled. 1 = payload descrambling is enabled. payload of cells received in the presync and sync states of cell delineation are descrambled, based on the self-synchronizing polynomial x 43 + 1. the cell header is unaffected by descrambling. bit 3: receive pass hec-errored cells (rphec) 0 = DS26102 passes only error-free and error-corrected cells to the atm layer. 1 = DS26102 passes all received cells, including hec errored cells to the atm layer when cell delineation is in sync. bit 4: receive idle cell-filter enable (ricfe) 0 = DS26102 does not filter idle cells. 1 = DS26102 filters all idle cells received from being written into receive fifo. the cell header of idle cell (first 5 bytes) is 0x00, 0x00, 0x00, 0x01, and proper hec byte. cell payload is not considered for idle cell filtering. bit 5: receive unassigned cell-filter enable (rucfe) 0 = DS26102 does not filter unassigned cells. 1 = DS26102 filters all unassigned cells received from being written into receive fifo. the cell header of unassigned cell (first five bytes) is 0x00, 0x00, 0x00, 0x00 and proper hec byte. cell payload is not considered for unassigned cell filtering.* bit 6: receive parity select (rprs). this bit determines the parity type for the ur_par signal. 0 = odd parity calculated for receive utopia bus 1 = even parity calculated for receive utopia bus bit 7: unassigned, must be set to 0 for proper operation * the header pattern of an unassigned cell is 0x00, 0x00, 0x00, 0x00, and proper hec byte. the header pattern of an idle cell is 0x00, 0x00, 0x00, 0x01, and proper hec byte for the first 4 bytes. note that, for cell filtering, only the header pattern (payload is don?t care) is checked.
DS26102 16-port tdm-to-atm phy 38 of 64 register name: rcr2 register description: receive control register 2 register address: 1ah, 3ah, 5ah, 7ah, 9ah, bah, dah, fah bit: 7 6 5 4 3 2 1 0 name: ? ? exstatim lcdim rfoim raes rplim dlbe default: 0 0 0 0 0 0 0 0 bit 0: diagnostic loopback enable (dlbe) 0 = normal operation 1 = diagnostic loopback is enabled. in this loopback, the transmit data and clock is looped back onto the receive side. the rx physical interface mode should be configured with the same value as the tx physical interface mode. the rx active-edge selection bit should be configured as the opposite edge of that used by the transmit section of the DS26102. it is possible to use the internally generated sys_clk/8 in place of tclk for this mode, enabled with (tcr2.6). bit 1: receive physical-layer interface mode (rplim) 0 = clock + data + frame-pulse combination 1 = gapped clock + data combination bit 2: receive active clock-edge selection (raes) 0 = positive edge of receive line clock is used for sampling input line signals. 1 = negative edge of receive line clock is used for sampling. bit 3: receive fifo overrun interrupt mask (rfoim) 0 = DS26102 does not generate an external interrupt for receive fifo-overrun events. 1 = DS26102 generates an external interrupt if a receive fifo-overrun condition has occurred. bit 4: lcd interrupt mask (lcdim) 0 = DS26102 does not generate external interrupt for lcd state changes. 1 = DS26102 does generate an external interrupt if the lcd state has changed. bit 5: external status event interrupt mask (exstatim) 0 = DS26102 does not generate an external interrupt on the exstat signal. 1 = DS26102 generates an external interrupt on the rising edge of the exstat signal associated with the enabled port. bits 6, 7: unassigned, must be set to 0 for proper operation 10.3.1 additional receive control information the active edge of the line clock used for sampling the input signals from the physical layer, namely data and frame-pulse-indication signals, are programmed to use the opposite edge of the active edge, which is used by the physical layer (framer). for example, if the physical layer uses the positive edge of the receive line clock to launch data and frame-pulse-indication signals, then the receive active-line clock-edge selection bit is programmed to 1, so that the receive line interface block uses the negative edge to sample the incoming signals. in diagnostic loopback, the receive active-line clock edge is programmed to use the opposite edge as that of the transmit interface. so, the receive active-line clock-edge selection (raes) is programmed inverted from the transmit active- line clock-edge selection (taes) during diagnostic loopback. the receive physical-layer interface mode determines the protocol used in the receive interface for sampling data bits. in gapped clock and data combination, the data bits are sampled at every line clock. the receive line clock is gapped at the framing-overhead-bit location. in clock, data, and frame-pulse-indication combination, data bits coming with frame-pulse indication asserted are ignored in the t1 case. in the e1 case, frame-pulse indication is used to locate ts0 and ts16 slots, and data bits coming at these time slots are ignored. in the clear e1 case, the interface should be configured in gapped clock and data combination even though the clock may not be gapped.
DS26102 16-port tdm-to-atm phy 39 of 64 for clear e1, data bits are sampled by the receive section at every clock tick, and the external frame-pulse indication is ignored. the receive fifo-overrun condition indicates that the receive fifo has been filled with 4 cells before the atm layer has read the fifo. the four cells that caused the receive fifo-overrun condition remain intact in the receive fifo, and subsequent cells are not written into memory until the atm layer reads at least one cell through the utopia ii interface. register name: rlcdip register description: receive lcd integration period register address: 11h (common for all receive ports) bit: 7 6 5 4 3 2 1 0 name: rlip7 rlip6 rlip5 rlip4 rlip3 rlip2 rlip1 rlip0 default: 0 1 1 0 0 1 1 0 bits 0 to 7: receive lcd integration period (rlip0 to rlip7). this 8-bit register holds the value of the lcd integration period (the time the cell delineation condition must persist before the DS26102 declares lcd). the DS26102 also deasserts the lcd indication once cell delineation is maintained in the sync state for the amount of time programmed in this register. lcd state-change condition can be programmed to generate an external interrupt through rcr2.4. a value of 0 programmed into this r egister declares lcd for every ocd condition at the resolution of the internal system clock period x 16,383. the value to be used in this register can be determined as follows: register value to be programmed = (integration time needed) / (system clock period x 16,383) e.g., for a system clock period of 60ns and desired integration time of 100ms, the register value should be: 100,000,000ns / (60ns x 16,383) = 66h register name: rpcl register description: receive-pmon counter latch enable register address: 12h, 32h, 52h, 72h, 92h, b2h, d2h, f2h bit: 7 6 5 4 3 2 1 0 name: ? ? ? ? ? ? ? ? default: 0 0 0 0 0 0 0 0 bits 0 to 7: the host should always write 0x00 to this register when latching the receive pmon counter. writing 0x00 to this register latches all receive-pmon counter values for the given port. namely, the 16-bit receive- assigned cell-count value, 12-bit receive uncorrectable hec-count value, and 8-bit receive correctable hec-count value of a port is latched into the associated registers. a write into this register also clears the receive pmon counters for that port. figure 10-2 depicts the sequence of operation to be performed for accessing rx pmon counters for a port. for example, if port 8?s (one-based) rx-assigned cell-count value is to be read, software must first write into rx- pmon counter-latch enable register at 0xf2 and then read from rx-assigned cell counter msb-latch register at 0xf6 and rx-assigned cell counter lsb register at 0xf7. note that all rx pmon counters maintained for port 8 are reset as the rpcl register is accessed. thus, it is recommended that all rx pmon counters be read together by following the sequence depicted in figure 10-2 .
DS26102 16-port tdm-to-atm phy 40 of 64 figure 10-2. accessing rx pmon counters how the ds26101/DS26102 responds ds26101/DS26102 latch all rx pmon counter values of the port selected into corresponding latch registers and clear a ll internal pmon counters of the port for fresh accumulation. ds26101/DS26102 drive latched correctable hec count value (rchec[7:0]) into the microprocessor data bus. ds26101/DS26102 drive the four most significant bits of the latched uncorrectable hec count value (ruhec[11:8]) onto the data bus. ds26101/DS26102 drive the least significant 8 bits of the latched uncorrectable hec count value (ruhec[7:0]) onto the data bus. ds26101/DS26102 drive the most significant 8 bits of the assigned cell-count value (racc[15:8]) onto the data bus. ds26101/DS26102 drive the least significant 8 bits of the assigned cell-count value (racc[7:0]) onto the data bus. what the host must do write 00 into rx-pmon counter latch- enable register (rpcl) for the por t whose counter values are to be obtained. note that only the address specific to the intended port is used. read from rx-correctable hec counter l a tch register (rchec). note that any one of the eight addresses specified can be used. read from rx-uncorrectable he c counter msb latch register (ruhec1). note that any one of the eigh t addresses specified can be used. read from rx-uncorrectable he c counter lsb latch register (ruhec2). note that any one of the eigh t addresses specified can be used. read from rx- a ssigned cell counte r msb latch register (racc1). note tha t a ny one of the eight addresses specified can be used. read from rx- a ssigned cell counte r lsb latch register (racc2). note tha t a ny one of the eight addresses specified can be used.
DS26102 16-port tdm-to-atm phy 41 of 64 register name: rchec register description: receive correctable-hec counter register address: 13h, 33h, 53h, 73h, 93h, b3h, d3h, f3h (common to all ports) bit: 7 6 5 4 3 2 1 0 name: rchc7 rchc6 rchc5 rchc4 rchc3 rchc2 rchc1 rchc0 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive correctab le-hec counter (rchc0 to rchc7). this register holds the number of correctable hec-errored cells received since the last latching. note that this count corresponds to cells received when cell delineation is in sync. a correctable hec-errored cell is a cell with single-bit error, provided single-bit hec error correction is enabled through rcr1.1 and the receiver mode of operation is in correction mode. correctable-hec count value is not affected if hec-error correction is disabled. register name: ruhec1 register description: receive uncorrectable-hec counter register 1 register address: 14h, 34h, 54h, 74h, 94h, b4h, d4h, f4h (common to all ports) bit: 7 6 5 4 3 2 1 0 name: ? ? ? ? ruhc11 ruhc10 ruhc9 ruhc8 default: 0 0 0 0 0 0 0 0 bits 0 to 3: receive uncorrectab le-hec counter (ruhc8 to ruhc11) bits 4 to 7: unused register name: ruhec2 register description: receive uncorrectable-hec counter register 2 register address: 15h, 35h, 55h, 75h, 95h, b5h, d5h, f5h (common to all ports) bit: 7 6 5 4 3 2 1 0 name: ruhc7 ruhc6 ruhc5 ruhc4 ruhc3 ruhc2 ruhc1 ruhc0 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive uncorrectab le-hec counter (ruhc0 to ruhc7). the ruhec1 and ruhec2 registers count the number of uncorrectable hec-errored cells received since the last latching. note that this count corresponds to cells received when cell delineation is in sync. for every sync-to-hunt transition of the cell delineation state machine, the ?correctable + uncorrectable? error-count value increases by 6 instead of 7. if hec correction is enabled, for every sync-to-hunt transition, the correctable hec count increases by 1 and the uncorrectable hec count increases by 5. if hec correction is disabled, correctable hec count is not affected and uncorrectable hec count increases by 6. note that upon the reception of the 7th consecutive hec pattern, cell delineation goes to hunt state. receive pmon counters are not updated when cell delineation is out of sync state. note that write access to the rpcl register latches internal receive-pmon values and clear the counters. uncorrectable hec-error cell means: if hec-error correction is enabled (rhece = 1) { cell with multibit hec error in cell header or cell with single-bit hec error in cell header, provided receiver mode of operation is in detection mode } else { cell with either single bit or multibit hec error in cell header } note that this count corresponds to cells received when cell delineation is in sync.
DS26102 16-port tdm-to-atm phy 42 of 64 register name: racc1 register description: receive-assigned cell-count register 1 register address: 16h, 36h, 56h, 76h, 96h, b6h, d6h, f6h (common to all ports) bit: 7 6 5 4 3 2 1 0 name: racc15 racc14 racc13 racc1 2 racc11 racc10 racc9 racc8 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive-assigned cell count 8 to 15 (racc8 to racc15) register name: racc2 register description: receive-assigned cell-count register 2 register address: 17h, 37h, 57h, 77h, 97h, b7h, d7h, f7h (common to all ports) bit: 7 6 5 4 3 2 1 0 name: racc7 racc6 racc5 racc4 racc3 racc2 racc1 racc0 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive-assigned cell count 0 to 7 (racc0 to racc7). the racc1 and racc2 registers are common registers for all ports. for software convenience, any of the eight addresses can be used to access these registers. for reading the 16-bit receive-assigned cell count for a port, software must write into the rpcl register for the port before reading from these registers. reading from these registers without writing into the latch-enable register returns the old value that was latched and not the current value of the receive-assigned cell count of a port. the assigned cell-count value reflects the number of cells written into the receive fifo that can be read by the atm layer since last latching. note that, whether or not the atm layer dequeues cells from the receive fifo, the assigned cell counter of a port is incremented upon the reception of a valid atm layer cell, as long as the cell delineation is in sync state. a valid atm layer cell is defined as: if (hec-errored cells are programmed to be passed to atm layer (rphec = 1)) { cell received when cell delineation is in sync state } else { cell with correct hec or if (hec-error correction is enabled (rhece=1)) { cell with single-bit hec error in cell header, provided receiver mode is in correction } } note that this count corresponds to cells received when cell delineation is in sync.
DS26102 16-port tdm-to-atm phy 43 of 64 10.3.2 user-programmable cell filtering user-programmable cell filtering allows the user to define a maskable pattern for each of the 4 bytes in the cell header so that the DS26102 either filters (rejects) all matching receive cells, or alternately only accepts cells that match the predefined pattern. five registers are defined for this function per port. this function is an addition to the DS26102?s ability to filter standard idle/unassigned cells. the user must program a filter pattern in the rufpm1?4 registers by setting the ufpms (rufc.2) bit = 0, then program the mask, or ?don?t care? pattern, in the rufpm1?4 registers by setting the ufpms bit = 1. register name: rufc register description: receive user-filter control register address: 1bh, 3bh, 5bh, 7bh, 9bh, bbh, dbh, fbh bit: 7 6 5 4 3 2 1 0 name: ? ? ? ? ? ufpms ufms ufen default: 0 0 0 0 0 0 0 0 bit 0: user-filter enable (ufen) 0 = do not apply the user-defined filter. 1 = filter incoming cells based on the ufpm registers bit 1: user-filter-mode select (ufms) 0 = reject (block) all cells that match the user-defined pattern and mask. 1 = accept (pass) only the cells that match the user-defined pattern and mask. bit 2: user-filter pattern/mask select (ufpms). this bit must be set = 0 to enter the filter pattern, and then set = 1 to enter the filter mask. 0 = user-filter pattern/mask (ufpm) registers are enabled as pattern mode. 1 = user-filter pattern/mask (ufpm) registers are enable as mask mode. bits 3 to 7: unassigned, must be set to 0 for proper operation register name: rufpm1 register description: receive user-filter pattern/mask register 1 register address: 1ch, 3ch, 5ch, 7ch, 9ch, bch, dch, fch bit: 7 6 5 4 3 2 1 0 name: h1.7 h1.6 h1.5 h1.4 h1.3 h1.2 h1.1 h1.0 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive user-filter pattern/mask 1 (ufpm1[7:0]). when ufpms = 0, this register can be programmed with the cell header pattern to match with the first octet (h1) of the received atm cell. when ufpms = 1, this register can be programmed with cell header mask associated with the first octet (h1). a logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. an ffh in this register enables matching of all 8 bits in pattern register 1. a logic 0 causes the masking of the corresponding bit (essentially a don?t care in the match).
DS26102 16-port tdm-to-atm phy 44 of 64 register name: rufpm2 register description: receive user-filter pattern/mask register 2 register address: 1dh, 3dh, 5dh, 7dh, 9dh, bdh, ddh, fdh bit: 7 6 5 4 3 2 1 0 name: h2.7 h2.6 h2.5 h2.4 h2.3 h2.2 h2.1 h2.0 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive user-filter pattern/mask 2 (ufpm2[7:0]). when ufpms = 0, this register can be programmed with the cell header pattern to match with the second octet (h2) of the received atm cell. when ufpms = 1, this register can be programmed with the cell header mask associated with the second octet (h2). a logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. an ffh in this register enables matching of all 8 bits in pattern register 2. a logic 0 causes the masking of the corresponding bit (essentially a don?t care in the match). register name: rufpm3 register description: receive user-filter pattern/mask register 3 register address: 1eh, 3eh, 5eh, 7eh, 9eh, beh, deh, feh bit: 7 6 5 4 3 2 1 0 name: h3.7 h3.6 h3.5 h3.4 h3.3 h3.2 h3.1 h3.0 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive user-filter pattern/mask 3 (ufpm3[7:0]). when ufpms = 0, this register can be programmed with the cell header pattern to match with the third octet (h3) of the received atm cell. when ufpms = 1, this register can be programmed with the cell header mask associated with the third octet (h3). a logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. an ffh in this register enables matching of all 8 bits in pattern register 3. a logic 0 causes the masking of the corresponding bit (essentially a don?t care in the match). register name: rufpm4 register description: receive user-filter pattern/mask register 4 register address: 1fh, 3fh, 5fh, 7fh, 9fh, bfh, dfh, ffh bit: 7 6 5 4 3 2 1 0 name: h4.7 h4.6 h4.5 h4.4 h4.3 h4.2 h4.1 h4.0 default: 0 0 0 0 0 0 0 0 bits 0 to 7: receive user-filter pattern/mask 4 (ufpm4[7:0]). when ufpms = 0, this register can be programmed with the cell header pattern to match with the fourth octet (h4) of the received atm cell. when ufpms = 1, this register can be programmed with the cell header mask associated with the fourth octet (h4). a logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. an ffh in this register enables matching of all 8 bits in pattern register 4. a logic 0 causes the masking of the corresponding bit (essentially a don?t care in the match).
DS26102 16-port tdm-to-atm phy 45 of 64 11. jtag boundary scan architecture and test access port the DS26102 ieee 1149.1 design supports the standard instruction codes sample/preload, bypass, and extest. optional public instructions included are highz, clamp, and idcode ( table 11-a ). the DS26102 contains the following functions, as required by ieee 1149.1 standard test access port and boundary scan architecture. test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the tap has the necessary interface pins jtrst, jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details. figure 11-1. jtag functional block diagram jtdi jtms jtclk jtrst jtdo test access port controller v dd v dd v dd boundry scan register bypass register instruction register identification register mux select output enable 10k ? 10k ? 10k ?
DS26102 16-port tdm-to-atm phy 46 of 64 tap controller state machine. the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk ( figure 11-2 ). test-logic-reset. upon power-up, the tap controller is in the test-logic-reset state. the instruction register contains the idcode instruction. all system logic of the device operates normally. run-test-idle. the run-test-idle is used between scan operations or during specific tests. the instruction register and test registers remain idle. select-dr-scan. all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and initiates a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir-scan state. capture-dr. data can be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. on the rising edge of jtclk, the controller goes to the shift-dr state if jtms is low or it goes to the exit1-dr state if jtms is high. shift-dr. the test data register selected by the current instruction is connected between jtdi and jtdo and shifts data one stage toward its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. exit1-dr. while in this state, a rising edge on jtclk puts the controller in the update-dr state, which terminates the scanning process, if jtms is high. a rising edge on jtclk with jtms low puts the controller in the pause- dr state. pause-dr. shifting of the test registers is halted while in this state. all test registers selected by the current instruction retain their previous state. the controller remains in this state while jtms is low. a rising edge on jtclk with jtms high puts the controller in the exit2-dr state. exit2-dr. a rising edge on jtclk with jtms high while in this state puts the controller in the update-dr state and terminates the scanning process. a rising edge on jtclk with jtms low enters the shift-dr state. update-dr. a falling edge on jtclk while in the update-dr state latches the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output because of changes in the shift register. select-ir-scan. all test registers retain their previous state. the instruction register remains unchanged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture-ir state and initiates a scan sequence for the instruction register. jtms high during a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir. the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller enters the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller enters the shift-ir state. shift-ir. in this state, the shift register in the instruction register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk toward the serial output. the parallel register as well as all test registers remains at their previous states. a rising edge on jtclk with jtms high moves the controller to the exit1-ir state. a rising edge on jtclk with jtms low keeps the controller in the shift-ir state while moving data one stage thorough the instruction shift register. exit1-ir. a rising edge on jtclk with jtms low puts the controller in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller enters the update-ir state and terminates the scanning process. pause-ir. shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk puts the controller in the exit2-ir state. the controller remains in the pause-ir state if jtms is low during a rising edge on jtclk.
DS26102 16-port tdm-to-atm phy 47 of 64 exit2-ir. a rising edge on jtclk with jtms low puts the controller in the update-ir state. the controller loops back to shift-ir if jtms is high during a rising edge of jtclk in this state. update-ir. the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jtms low puts the controller in the run-test-idle state. with jtms high, the controller enters the select-dr-scan state. figure 11-2. tap controller state diagram 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
DS26102 16-port tdm-to-atm phy 48 of 64 11.1 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction shift register is connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low shifts the data one stage toward the serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the exit2-ir state with jtms high moves the controller to the update-ir state. the falling edge of that same jtclk latches the data in the instruction shift register to the instruction parallel output. instructions supported by the DS26102 and its respective operational binary codes are shown in table 11-a . table 11-a. instruction codes for ieee 1149.1 architecture instruction selected regi ster instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 sample/preload. this is a mandatory instruction for the ieee 1149.1 specification that supports two functions. the digital i/os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-dr state. sample/preload also allows the device to shift data into the boundary scan register through jtdi using the shift-dr state. bypass. when the bypass instruction is latched into the parallel instruction register, jtdi connects to jtdo through the 1-bit bypass test register. this allows data to pass from jtdi to jtdo without affecting the device?s normal operation. extest. this instruction allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled through the update-ir state, the parallel outputs of all digital output pins are driven. the boundary scan register is connected between jtdi and jtdo. the capture-dr samples all digital inputs into the boundary scan register. clamp. all digital outputs of the device output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs do not change during the clamp instruction. highz. all digital outputs of the device are placed in a high-impedance state. the bypass register is connected between jtdi and jtdo. idcode. when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code is loaded into the identification register on the rising edge of jtclk following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially through jtdo. during test-logic-reset, the identification code is forced into the instruction register?s parallel output. the id code always has a 1 in the lsb position. the next 11 bits identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. table 11-b. id code structure msb lsb (must be 1) version?contact factory device id jedec 1 4 bits see table 11-c 00010100001 1 table 11-c. device id codes part id code DS26102 0000000000100111
DS26102 16-port tdm-to-atm phy 49 of 64 11.2 test registers ieee 1149.1 requires a minimum of two test registers?the bypass register and the boundary scan register. an optional test register, the identification register, has been included with the DS26102 design. it is used in conjunction with the idcode instruction and the test-logic-reset state of the tap controller. bypass register. this is a single one-bit shift register used in conjunction with the bypass, clamp, and highz instructions. it provides a short path between jtdi and jtdo. boundary scan register. this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells. it is n bits in length. see table 11-d for the cell bit locations and definitions. identification register. the identification register contains a 32-bit shift register and a 32-bit latched parallel output. this register is selected during the idcode instruction and when the tap controller is in the test-logic- reset state. table 11-d. boundary scan control bits cell name type control cell 0 ? controlr 1 tfp13 output3 0 2 tfp13 observe_only 3 tclk13 observe_only 4 tdata13 output3 161 5 ? controlr 6 tfp12 output3 5 7 tfp12 observe_only 8 tclk12 observe_only 9 tdata12 output3 161 10 ? controlr 11 tfp11 output3 10 12 tfp11 observe_only 13 tclk11 observe_only 14 tdata11 output3 161 15 ? controlr 16 tfp10 output3 15 17 tfp10 observe_only 18 tclk10 observe_only 19 tdata10 output3 161 20 ? controlr 21 tfp9 output3 20 22 tfp9 observe_only 23 tclk9 observe_only 24 tdata9 output3 161 25 ? controlr 26 tfp8 output3 25 27 tfp8 observe_only 28 tclk8 observe_only 29 tdata8 output3 161 30 rfp15 observe_only 31 rclk15 observe_only 32 rdata15 observe_only 33 rfp14 observe_only 34 rclk14 observe_only 35 rdata14 observe_only 36 rfp13 observe_only 37 rclk13 observe_only 38 rdata13 observe_only 39 rfp12 observe_only 40 rclk12 observe_only cell name type control cell 41 rdata12 observe_only 42 rfp11 observe_only 43 rclk11 observe_only 44 rdata11 observe_only 45 rfp10 observe_only 46 rclk10 observe_only 47 rdata10 observe_only 48 rfp9 observe_only 49 rclk9 observe_only 50 rdata9 observe_only 51 rfp8 observe_only 52 rclk8 observe_only 53 rdata8 observe_only 54 rlcd15 output3 161 55 rlcd14 output3 161 56 rlcd13 output3 161 57 rlcd12 output3 161 58 rlcd11 output3 161 59 rlcd10 output3 161 60 rlcd9 output3 161 61 rlcd8 output3 161 62 rlcd7 output3 161 63 rlcd6 output3 161 64 rlcd5 output3 161 65 rlcd4 output3 161 66 rlcd3 output3 161 67 rlcd2 output3 161 68 rlcd1 output3 161 69 rlcd0 output3 161 70 ur_par output3 77 71 ur_clav3 output3 73 72 ur_clav2 output3 73 73 ? controlr 74 ur_clav1 output3 73 75 ? controlr 76 ur_clav0 output3 75 77 ? controlr 78 ur_soc output3 77 79 ur_data0 output3 86 80 ur_data1 output3 86 81 ur_data2 output3 86
DS26102 16-port tdm-to-atm phy 50 of 64 cell name type control cell 82 ur_data3 output3 86 83 ur_data4 output3 86 84 ur_data5 output3 86 85 ur_data6 output3 86 86 ? controlr 87 ur_data7 output3 86 88 ur_clk observe_only 89 ur_enb observe_only 90 ur_addr0 observe_only 91 ur_addr1 observe_only 92 ur_addr2 observe_only 93 ur_addr3 observe_only 94 ur_addr4 observe_only 95 ut_2clav3 output3 100 96 ut_2clav2 output3 100 97 ut_2clav1 output3 100 98 ut_clav3 output3 100 99 ut_clav2 output3 100 100 ? controlr 101 ut_clav1 output3 100 102 ut_2clav0 output3 103 103 ? controlr 104 ut_clav0 output3 103 105 ut_par observe_only 106 ut_clk observe_only 107 ut_soc observe_only 108 ut_data0 observe_only 109 ut_data1 observe_only 110 ut_data2 observe_only 111 ut_data3 observe_only 112 ut_data4 observe_only 113 ut_data5 observe_only 114 ut_data6 observe_only 115 ut_data7 observe_only 116 ut_enb observe_only 117 ut_addr0 observe_only 118 ut_addr1 observe_only 119 ut_addr2 observe_only 120 ut_addr3 observe_only 121 ut_addr4 observe_only 122 ? controlr 123 tfp7 output3 122 124 tfp7 observe_only 125 tclk7 observe_only 126 tdata7 output3 161 127 ? controlr 128 tfp6 output3 127 129 tfp6 observe_only 130 tclk6 observe_only 131 tdata6 output3 161 132 ? controlr 133 tfp5 output3 132 134 tfp5 observe_only 135 tclk5 observe_only 136 tdata5 output3 161 137 ? controlr 138 tfp4 output3 137 139 tfp4 observe_only 140 tclk4 observe_only cell name type control cell 141 tdata4 output3 161 142 ? controlr 143 tfp3 output3 142 144 tfp3 observe_only 145 tclk3 observe_only 146 tdata3 output3 161 147 ? controlr 148 tfp2 output3 147 149 tfp2 observe_only 150 tclk2 observe_only 151 tdata2 output3 161 152 ? controlr 153 tfp1 output3 152 154 tfp1 observe_only 155 tclk1 observe_only 156 tdata1 output3 161 157 ? controlr 158 tfp0 output3 157 159 tfp0 observe_only 160 tclk0 observe_only 161 ? controlr 162 tdata0 output3 161 163 rfp7 observe_only 164 rclk7 observe_only 165 rdata7 observe_only 166 rfp6 observe_only 167 rclk6 observe_only 168 rdata6 observe_only 169 rfp5 observe_only 170 rclk5 observe_only 171 rdata5 observe_only 172 rfp4 observe_only 173 rclk4 observe_only 174 rdata4 observe_only 175 rfp3 observe_only 176 rclk3 observe_only 177 rdata3 observe_only 178 rfp2 observe_only 179 rclk2 observe_only 180 rdata2 observe_only 181 rfp1 observe_only 182 rclk1 observe_only 183 rdata1 observe_only 184 rfp0 observe_only 185 rclk0 observe_only 186 rdata0 observe_only 187 int output2 187 188 ? internal 189 int observe_only 190 bls0 observe_only 191 mux observe_only 192 bts observe_only 193 cs observe_only 194 wr ( r / w ) observe_only 195 rd ( ds) observe_only 196 d0/ad0 output3 210 197 d0/ad0 observe_only 198 d1/ad1 output3 210 199 d1/ad1 observe_only
DS26102 16-port tdm-to-atm phy 51 of 64 cell name type control cell 200 d2/ad2 output3 210 201 d2/ad2 observe_only 202 d3/ad3 output3 210 203 d3/ad3 observe_only 204 d4/ad4 output3 210 205 d4/ad4 observe_only 206 d5/ad5 output3 210 207 d5/ad5 observe_only 208 d6/ad6 output3 210 209 d6/ad6 observe_only 210 ? controlr 211 d7/ad7 output3 210 212 d7/ad7 observe_only 213 a0 observe_only 214 a1 observe_only 215 a2 observe_only 216 a3 observe_only 217 a4 observe_only 218 a5 observe_only 219 a6 observe_only 220 a7/ale (as) observe_only 221 exstat7 observe_only 222 exstat6 observe_only cell name type control cell 223 exstat5 observe_only 224 exstat4 observe_only 225 exstat3 observe_only 226 exstat2 observe_only 227 exstat1 observe_only 228 exstat0 observe_only 229 1secout output3 161 230 8khzin observe_only 231 gclkin observe_only 232 gclkout output3 161 233 refclkin observe_only 234 reset observe_only 235 ? controlr 236 tfp15 output3 235 237 tfp15 observe_only 238 tclk15 observe_only 239 tdata15 output3 161 240 ? controlr 241 tfp14 output3 240 242 tfp14 observe_only 243 tclk14 observe_only 244 tdata14 output3 161
DS26102 16-port tdm-to-atm phy 52 of 64 12. operating parameters absolute maximum ratings voltage range on any pin with respect to v ss (except v dd ) -0.3v to +5.5v supply voltage (v dd ) range with respect to v ss -0.3v to +3.63v operating temperature range -40oc to +85oc storage temperature range -55oc to +125oc soldering temperature see ipc/jedec j-std-020a stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device. recommended dc operating conditions (t a = -40oc to +85oc) parameter symbol min typ max units logic 1 v ih 2.0 5.5 v logic 0 v il -0.3 +0.8 v supply v dd 3.135 3.3 3.465 v capacitance (t a = +25oc) parameter symbol min typ max units input capacitance c in 7 pf output capacitance c out 7 pf dc characteristics (v dd = 3.135v to 3.465v, t a = -40c to +85c.) parameter symbol min typ max units supply current at 3.3v (note 2) i dd 85 ma input leakage i il -10.0 +10.0 a tri-state output leakage i ol -10.0 +10.0 a output voltage (i o = -4.0ma) (note 3) v oh 2.4 v output voltage (i o = +4.0ma) (note 3) v ol 0.4 v utopia v oh (i o = -8.0ma) (note 4) v ohu 2.4 v utopia v ol (i o = +8.0ma) (note 4) v olu 0.4 v note 1: theta-ja is based on the package mounted on a 4-layer jedec board and measured in a jedec test chamber. note 2: rclk1 - n = tclk1 - n = 2.048mhz, gclk = 32.768mhz. note 3: applies to all non-utopia outputs. note 4: applies to utopia outputs.
DS26102 16-port tdm-to-atm phy 53 of 64 13. critical timing information unless otherwise noted, all timing numbers assume 20pf test load on output signals, 40pf test load on bus signals. table 13-a. ac characteristics?multiplexed parallel port (mux = 1) (v dd = 3.3v 5%, t a = -40c to +85c.) ( figure 13-1 , figure 13-2 , and figure 13-3 ) parameter symbol min typ max units cycle time t cyc 200 ns pulse width, ds low or rd high pw el 100 ns pulse width, ds high or rd low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w hold time t rwh 10 ns r/w setup time before ds hig h t rws 50 ns cs setup time before ds , wr , or rd active t cs 20 ns cs hold time t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 5 ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr , or rd to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr , or rd t ased 10 ns output data delay time from ds or rd t ddr 80 ns data setup time t dsw 50 ns figure 13-1. intel bus read timing (bts = 0/mux = 1) ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased cs_b ad0-ad7 dhr t ddr ale (a7) rd_b wr_b
DS26102 16-port tdm-to-atm phy 54 of 64 figure 13-2. intel bus write timing (bts = 0/mux = 1) figure 13-3. motorola bus timing (bts = 1/mux = 1) ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased cs_b ad0-ad7 rd_b wr_b ale (a7) t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws ahl pw el t cyc as ds ad0-ad7 (write) ad0-ad7 (read) r/ w cs_b
DS26102 16-port tdm-to-atm phy 55 of 64 table 13-b. ac characteristics?nonmultiplexed parallel port (mux = 1) (v dd = 3.3v 5%, t a = -40c to +85c.) ( figure 13-4 through figure 13-7 ) parameter symbol min typ max units setup time for a[7:0], bls0 valid to cs active t1 0 ns setup time for cs active to either rd or wr active t2 0 ns delay time from either rd or ds active to d/ad[7:0] valid t3 130 ns hold time from either rd or wr inactive to cs inactive t4 0 ns hold time from cs or rd or ds inactive to d/ad[7:0] tri-state t5 5 25 ns wait time from wr active to latch data t6 30 ns data setup time to wr inactive t7 10 ns data hold time from wr inactive t8 2 ns address, bls0 hold from wr inactive t9 0 ns write access to subsequent write/read access delay time (note 1) t10 5 x gclk ns note 1: time t10 should be minimum 5 x the gclkin period. for a gclkin = 33mhz, t10 = 150ns. note 2: interrupt is deasserted at 5 x gclkin period + 40ns maximum from rd active. figure 13-4. intel bus read timing (bts = 0/mux = 0) t2 t3 address valid data valid t4 t9 t5 t10 addr[7:0] data[7:0] cs_b rd_b wr_b t1
DS26102 16-port tdm-to-atm phy 56 of 64 figure 13-5. intel bus write timing (bts = 0/mux = 0) figure 13-6. motorola bus read timing (bts = 1/mux = 0) figure 13-7. motorola bus write timing (bts = 1/mux = 0) t2 t6 address valid t4 t9 t10 addr[7:0] data[7:0] cs_b rd_b wr_b t7 t8 t1 t2 t3 address valid data valid t4 t9 t5 t10 addr[7:0] data[7:0] cs_b ds_b r/w_b t1 t2 t6 address valid t4 t10 a ddr[7:0] data[7:0] cs_b r/w_b ds_b t7 t8 t1 t9
DS26102 16-port tdm-to-atm phy 57 of 64 table 13-c. framer interface ac characteristics parameter symbol min typ max units rclk duty cycle 30 70 % rdata and rfp setup to rclk active edge t11 10 ns rdata and rfp hold from rclk active edge t12 2 ns tclk duty cycle 30 70 % output delay tdata and tfp from tclk active edge (note 3) t13 20 ns tfp setup time to tclk active edge (note 4) t14 10 ns tfp hold time from tclk active edge (note 4) t15 10 ns note 3: tfp is an output. note 4: tfp is an input. table 13-d. utopia transmit ac characteristics parameter symbol min typ max units ut_clk frequency 0 25 mhz ut_clk duty cycle 40 60 % setup time ut_data[x], ut_addr[x], ut_enb , ut_soc, ut_par inputs to ut_clk t20 (ts) 10 ns hold time ut_data[x], ut_addr[x], ut_enb , ut_soc, ut_par inputs from ut_clk t21 (th) 1 ns output delay ut_clav[x] from ut_clk t22 (td) 20 ns output tri-state delay ut_clav[x] from ut_clk t23 (tz) 25 ns table 13-e. utopia receive ac characteristics parameter symbol min typ max units ur_clk frequency 0 25 mhz ur_clk duty cycle 40 60 % setup time ur_addr[x] and ur_enb inputs to ur_clk t24 (ts) 10 ns hold time ur_addr[x] and ur_enb inputs from ur_clk t25 (th) 1 ns output delay ur_clav[x], ur_data[x], ur_soc, and ur_par from ur_clk t26 (td) 20 ns output tri-state delay ur_clav[x], ur_data[x], ur_soc, and ur_par from ur_clk t27 (tz) 25 ns
DS26102 16-port tdm-to-atm phy 58 of 64 figure 13-8. setup/hold time definition figure 13-9. delay time definition table 13-f. jtag interface timing (v dd = 3.3v 5%, t a = -40c to +85c.) ( figure 13-10 ) parameter symbol min typ max units jtclk clock period t1 1000 ns jtclk clock high/low time (note 5) t2/t3 50 500 ns jtclk to jtdi, jtms setup time t4 3 ns jtclk to jtdi, jtms hold time t5 2 ns jtclk to jtdo delay t6 2 50 ns jtclk to jtdo high-z delay t7 2 50 ns jtrst width low time t8 100 ns note 5: clock can be stopped high or low. figure 13-10. jtag interface timing diagram clock signal ts th input setup to clock input hold from clock clock signal td and tz jtcl k t1 jtd0 t4 t5 t2 t3 t7 jtdi, jtms, jtrs t t6 jtrst t8
DS26102 16-port tdm-to-atm phy 59 of 64 table 13-g. system clock ac characteristics parameter symbol conditions min typ max units 1.544 refclkin frequency 2.048 mhz refclkin duty cycle 40 60 % gclk frequency (note 6) 16 40 mhz gclk duty cycle 40 60 % note 6: gclk frequency must be at least 10 times the line rate (either 1.544mhz or 2.048mhz). 14. thermal information table 14-a. thermal properties, natural convection parameter symbol conditions min typ max units ambient temperature (note 1) -40c +85c junction temperature -40c +125c theta - ja ( ja ), still air (note 2) 20.27c/w psi-jb 8.27c/w psi-jt 0.24c/w note 1: the package is mounted on a 4 - layer jedec standard test board with no airflow and dissipating maximum power. note 2: theta - ja ( ja ) is the junction to ambient thermal resistance, when the package is mounted on a 4 - layer jedec standard test board with no airflow and dissipating maximum power. table 14-b. theta - ja ( ja ) vs. airflow forced air (m/s) theta-ja ( ja ) 0 20.27c/w 1 17.44c/w 2.5 16.18c/w
DS26102 16-port tdm-to-atm phy 60 of 64 15. applications information 15.1 application in atm user-network interfaces figure 15-1 shows the application of the DS26102 in an atm user-network interface (uni). in a uni, the DS26102 provides the transmission convergence sublayer functionality. the interface between the DS26102 and the atm layer is governed by utopia ii specification from the atm forum. multiplexing with 1clav can be used as utopia polling mode. the DS26102 supports up to 16 t1/e1 ports. for cell-rate decoupling, 4-cell buffer is allocated per port separately in the transmit and receive interfaces with the atm layer. the buffer size of the transmit fifo is configurable to 2, 3, or 4 cells. this flexibility in changing the fifo depth provides users the control over cell latency, if desired. figure 15-1. user-network interface application 15.2 interfacing with framers figure 15-2 shows two methods of interfacing the DS26102 to a dallas framer. one method shows a ?loop timing? method where tclk, tsync/tfpx, rfpx, and rclk are derived from the receive framer?s rclk and rsync. the other method shows an interface where transmit and receive are independent. the following guidelines are suggested: tclk may be derived from rclk. tclk must be 1.544mhz for t1 and 2.048mhz for e1. the framer elastic stores should be disabled on both transmit and receive sides. rsync must be configured as a frame-boundary output. the framer tsync can be an input or an output (the DS26102 must be programmed accordingly). tsync should be configured for frame-boundary mode. the tsync and rsync signals should be high for only one tclk and rclk period, respectively. a tm layer DS26102 t1/e1 framer 1 t1/e1 framer 2 t1/e1 framer 16
DS26102 16-port tdm-to-atm phy 61 of 64 figure 15-2. DS26102 interfacing with dallas framer in framing-pulse mode when interfacing to framers where the framing pulse and data-active edge are individually configurable, ensure that the sampling and updating happen in opposite edges. table 15-a demonstrates the recommended configurations for interfacing the DS26102 to the framer signals. table 15-a. suggested clo ck edge configurations data update edge in DS26102 data-sampling edge in framer framing-pulse direction framing-pulse edge in framer positive negative from DS26102 to framer negative for sampling negative positive from DS26102 to framer positive for sampling positive negative from framer to DS26102 positive for updating negative positive from framer to DS26102 negative for updating 15.3 fractional t1/e1 support table 15-b describes the configuration needed by the DS26102 for supporting fractional t1/e1. note that in e1 mode, the DS26102 must be used in gapped-clock mode, where the clock is gapped during inactive channels as well as ts0 and ts16 for cas-framed format. when configured for t1, either frame-pulse or gapped-clock mode can be used, however, the tfp and rfp signals must be generated during framing overhead-bit and nonactive- ds0/ts positions of the t1 frame. older dallas framers may require additional logic to implement gapped-clock operation. table 15-b. fractional t1/e1 register settings control register bit t1 e1 tpc 0 1 tplim 0 for frame-pulse mode or 1 for gapped-clock mode 1 (gapped-clock mode only) tfsd 0 (input only) 0 for tfp as input or 1 for tfp as output rpc 0 1 rplim 0 for frame-pulse mode or 1 for gapped-clock mode 1 (gapped-clock mode only) DS26102 rclkx rdatax rfpx tclkx tdatax tfpx dallas framer rclk rser rsync tser tclk tsync DS26102 rclkx rdatax rfpx tclkx tdatax tfpx dallas framer rclk rser rsync tser tclk tsync clock x = 0 - 15 x = 0 - 15
DS26102 16-port tdm-to-atm phy 62 of 64 16. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .) note: all dimensions in millimeters.
DS26102 16-port tdm-to-atm phy 63 of 64 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .) bottom mechanical dimensions note: all dimensions in millimeters.
DS26102 16-port tdm-to-atm phy 64 of 64 17. revision history revision description 021403 new product release

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